FIN12ACMLX Fairchild Semiconductor, FIN12ACMLX Datasheet - Page 7

• Manufacturer Part Number: FIN12ACMLX
• Description: IC SERIALIZER/DESERIALIZER 32MLP
• Manufacturer: Fairchild Semiconductor
• Series: SerDes™r

Specifications of FIN12ACMLX

• Function: Serializer/Deserializer
• Data Rate: 560Mbps
• Input Type: LVCMOS
• Output Type: LVCMOS
• Number Of Inputs: 12
• Number Of Outputs: 12
• Voltage - Supply: 1.65 V ~ 3.6 V
• Operating Temperature: -30°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-MLP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: FIN12ACMLX; FIN12ACMLXTR

FIN12AC Rev. 1.1.2
© 2006 Fairchild Semiconductor Corporation
LVCMOS Data I/O
The LVCMOS input buffers have a nominal threshold
value equal to half V
operational when the device is operating as a serializer.
When the device is operating as a deserializer, the inputs
are gated off to conserve power.
The LVCMOS 3-STATE output buffers are rated for a
source / sink current of 2mA at 1.8V. The outputs are
active when the DIRI signal is asserted LOW. When the
DIRI signal is asserted HIGH, the bi-directional LVCMOS
I/Os are in HIGH-Z state. Under purely capacitive load
conditions, the output swings between GND and V
Application Mode Diagrams
Modes 1, 2, 3: Unidirectional Data Transfer
Figure 4. shows basic operation when a pair of µSerDes is configured in an unidirectional operation mode.
Master Operation:
1. During power-up, the device is configured as a
2. The device accepts CKREF_M word clock and gen-
3. The device receives parallel data on the rising edge
4. The device generates and transmits serialized data
5. The device generates an embedded word clock for
serializer based on the value of the DIRI signal.
erates a bit clock, which is sent to the slave device
through the CKSO port.
of STROBE_M.
on the DS signals, which is source synchronous with
CKSO.
each strobe signal.
STROBE_M
DP[1:12]_M
CKREF_M
Figure 4. Simplified Block Diagram for Unidirectional Serializer and Deserializer
Master Device Operating as a Serializer
DDP
. The input buffers are only
DIR = “1”
PLL
Serializer
Control
Serializer
BIT CK
Gen.
DDP
.
CKSO
+
–
+
–
DS
7
Slave Operation:
1. The device is configured as a deserializer at power-
2. The device accepts the bit clock on CKSI.
3. The device deserializes the DS data stream using the
4. The device writes parallel data onto the DP_S port
Serializer
Deserializer
CKSI
up based on the value of the DIRI signal.
CKSI input clock.
and generates the CKP_S only when a valid data
word occurs.
+
–
+
–
To
From
Slave Device Operating as a Deserializer
Control
Deserializer
Deserializer
From
Control
Figure 3.
Work CK
DIR = “0”
Gen
LVCMOS I/O
CKP_S
DP[1:12]_S
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DP[n]