FW82810 Q862 Intel, FW82810 Q862 Datasheet - Page 16

• Manufacturer Part Number: FW82810 Q862
• Manufacturer: Intel

Specifications of FW82810 Q862

• Lead Free Status / Rohs Status: Not Compliant

Intel
15.
Problem:
Implication: If the specific configuration and transaction sequence shown above occurs, the system may hang.
Workaround: Disable PCI pre-fetching in the ICH. This may cause a 1%-2% performance hit on PCI initiated
Status:
16.
Problem:
Implication: This is a violation of the PM 1.1 specification and causes the WHQL PC99A HCT9.x test to fail.
Workaround: None
Status:
17.
Problem:
Implication: When changing display surfaces using the asynchronous screen flipping, subtle display corruption
Workaround: Driver version 4.1.1 does, and future version will, disable asynchronous screen flipping for
Status:
16
®
82810 GMCH
Asynchronous Queue Overflow
A specific heavily loaded system configuration and specific traffic causes the 82810 GMCH
asynchronous queues to fill up, causing upbound I/O traffic to get blocked while waiting for an I/O
transaction to complete.
reads to DRAM only.
No planned silicon fix. A software fix to disable PCI pre-fetching will be published.
PM_CS Power State Bits Accept Invalid States
PCI Power Management Control/Status Register (PM_CS), Device 1, address offset E0h-E1h, bits
[1:0], accepts values representing power management states D1 and D2, which the hardware device
does not support.
This issue will not be fixed in the 82810 GMCH. Intel is working with Microsoft* on a WHQL
waiver for WHQL certification.
Asynchronous Screen Flip
When the Intel
under certain timing-dependent circumstances the display engine may temporarily read pixel data
from a random memory location.
is seen in the form of short, somewhat random colored, horizontal lines along the left side of the
screen.
commonly used 3D resolutions.
There are no plans to fix this erratum in silicon.
If the following specific configuration and transaction sequence occurs, the system may hang:
1.
2.
3.
4.
A CPU memory write to the hub interface occurs,
AND a QWord misaligned CPU read to PCI or LPC occurs
AND any three of the following four interfaces are simultaneously active,
queues in the GMCH.
AND sufficient system traffic exists to fill the asynchronous upbound and downbound
®
82810A2 or 82810A3 devices are configured for asynchronous screen flipping,
(2) IDE BM traffic to DRAM,
(4) PCI Master #2 read traffic from DRAM,
(1) PHLD traffic from M-ISA or LPC to DRAM,
(3) PCI Master #1 read traffic from DRAM,
Specification Update
R