PXB4220E-V33 Infineon Technologies, PXB4220E-V33 Datasheet - Page 204

• Manufacturer Part Number: PXB4220E-V33
• Description: IC CHIPSET 8 E1/T1 LINE 256-BGA
• Manufacturer: Infineon Technologies

Specifications of PXB4220E-V33

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 256-BGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: PXB4220E-V33; PXB4220E-V33IN

7.47
Read/Write Address 00104
Reset value: 0840
tur
pwd
lgc
lc8
lgs
lpcr
srt, acm
Data Sheet
tur(0]
15
7
Configuration Register Downstream of Port N (condN)
not used
pwd
Tuning range select of port N
The tuning range of PLL-ACM is limited to:
(frequency deviation of pin RFCLK in ppm) +/- ((4*tur) +/-5%)ppm.
Power down of port N
0 =
1 =
Loop back generated clock
0 =
1 =
Loop back clock 8.192 MHz
0 =
1 =
Loop back generated RTS
0 =
1 =
Loop back clock recovery Interface
0 =
1 =
Selectors for the clock generation algorithm
00 =
H
Normal operation
Power down mode. No RTS values and no transmit clock are
generated.
Normal operation
The clock generated by the PLL is looped into the RTS generator.
Normal operation
The receive clock is looped to the transmit output of the ICRC.
Normal operation
Generated RTS values are looped into the SRTS Receive FIFO.
Normal operation
The clock recovery interface is bypassed. RTS values from the
frame receiver are looped into the SRTS Transmit FIFO.
The PLL is put in power down mode, and a free running clock is
generated. In case pwd is set, all circuits of the port, including the
RTS generator are disabled, no output clock is generated and all
error counters are reset.
lgc
H
+ N x 32
lc8
204
PXB 4219E, PXB 4220E, PXB 4221E
lgs
tur[5:1]
lpcr
Register Description
srt
IWE8, V3.4
2003-01-20
acm
8
0