LTC4305IGN Linear Technology, LTC4305IGN Datasheet - Page 15

• Manufacturer Part Number: LTC4305IGN
• Description: IC BUFFER BUS 2WR ADDRESS 16SSOP
• Manufacturer: Linear Technology

Specifications of LTC4305IGN

• Applications: Multiplexer with Amplifier
• Interface: SMBus (2-Wire/I²C)
• Voltage - Supply: 2.2 V ~ 5.5 V
• Package / Case: 16-SSOP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIO S I FOR ATIO
Design Example
A typical LTC4305 application circuit is shown in Figure 5.
The circuit illustrates the level-shifting, multiplexer/switch
and capacitance buffering features of the LTC4305. In this
application, the LTC4305 V
bus 1 are powered from 3.3V, downstream bus 2 is
powered from 5V, and the upstream bus is powered from
2.5V. The following sections describe a methodology for
choosing the external components in Figure 5.
SDA, SCL Pull-Up Resistor Selection
The pull-up resistors on the SDA and SCL pins must be
strong enough to provide a minimum of 100µA pull-up
current, per the SMBus Specification. In most systems,
the required minimum strength of the pull-up resistors is
determined by the minimum slew requirement to guaran-
tee that the LTC4305’s rise time accelerators are activated
during rising edges. At the same time, the pull-up value
should be kept low to maximize the logic low noise margin
and minimize the offset voltage of the Upstream-Down-
stream Buffer circuitry. The LTC4305 is designed to
function for a maximum DC pull-up current of 4mA. If
multiple downstream channels are active at the same time,
this means that the sum total of the pull-up currents from
these channels must be less than 4mA. At supply voltages
of 2.7V and 5.5V, pull-up resistor values of 10k work well
for capacitive loads up to 215pF and 420pF, respectively.
CONTROLLER
MICRO-
U
U
CC
V
BACK
voltage and downstream
R1
10k
= 2.5V
W
R2
10k
R3
10k
Figure 5. A Level Shifting Circuit
10
U
5
3
2
9
8
4
SCLIN
SDAIN
ALERT
ADR2
ADR1
ADR0
GND
ADDRESS = 1000 100
LTC4305
7
V
CC
For larger bus capacitances, refer to equation (1) below.
The LTC4305 works with capacitive loads up to 2nF.
Assume in Figure 5 that the total parasitic bus capacitance
on SDA1 due to trace and device capacitance is 100pF. To
ensure that the boost currents are active during rising
edges, the pull-up resistor must be strong enough to
cause the SDA1 pin voltage to rise at a rate of 0.8V/µs as
the pin voltage is rising above 0.8V. The equation is:
where V
voltage, and C
example, V
tolerance, V
R
pull-up resistor smaller (i.e., stronger pull-up) than 27.1k,
so a 10k resistor works fine.
ALERT and READY Component Selection
The pull-up resistors on the ALERT and READY pins must
provide a maximum pull-up current of 3mA, so that the
LTC4305 is capable of holding the pins at logic low
voltages below 0.4V.
R
V
CC
ALERT1
ALERT2
PULL-UP,MAX
PULL UP MAX
SDA1
SDA2
SCL1
SCL2
= V
C1
0.01µF
BUS1
−
12
13
14
16
15
1
BUSMIN
= 3.3V
,
BUS1
R4
10k
R7
10k
BUS1MIN
[ ]
BUS
= 27.1kΩ. Therefore, we must choose a
k
is the minimum operating pull-up supply
= V
Ω
R5
10k
R8
10k
is the bus parasitic capacitance. In our
CC
=
⎧
⎨
⎩
= 3.3V, and assuming ±10% supply
V
(
= 2.97V. With C
R6
10k
R9
10k
BUS2
V
BUSMIN
= 5V
ADDRESS = 1111 000
ADDRESS = 1111 001
MODULE #1
MODULE #2
– .
C
SFP
SFP
BUS
0 8
V
[ ]
4305 F05
pF
) •
LTC4305
1250
BUS
⎡
⎢
⎣
= 100pF,
ns
V
15
⎤ ⎤
⎥
⎦
⎫
⎬
⎭
4305f
(1)