IDT77V011L155DA IDT, Integrated Device Technology Inc, IDT77V011L155DA Datasheet
IDT77V011L155DA
Specifications of IDT77V011L155DA
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IDT77V011L155DA Summary of contents
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Single chip interface between multiple UTOPIA PHYs and ...
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IDT77V011 % ...
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IDT77V011 ...
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IDT77V011 RxDATA [10] 103 I RxDATA [11] 104 I RxDATA [12] 105 I RxDATA [13] 106 I RxDATA [14] 107 I RxDATA [15] 110 I RSOC 111 I RCLAV 112 I RENB 121 O RxADDR [0] 120 O RxADDR [1] ...
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IDT77V011 TxDATA [11 TxDATA [12] 143 O TxDATA [13] 142 O TxDATA [14] 141 O TxDATA [15] 140 O TSOC 134 O TCLAV 126 I TENB 138 O TxADDR[0] 129 O I TxADDR[1] 130 O I TxADDR[2] 131 ...
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IDT77V011 MBUS[ MBUS[ MBUS[ MBUS[ MBUS[ MBUS[ MBUS[ MBUS[ MBUS[10 MBUS[11 ...
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IDT77V011 MDATA[3] 84 I/O MDATA[4] 85 I/O MDATA[5] 86 I/O MDATA[6] 87 I/O MDATA[7] 88 I/O MGMT[ MGMT[ MGMT[ MGMT[ MGMT[ PHYRST 74 O PHYINT 71 I SYSRST ...
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IDT77V011 $ ...
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IDT77V011 ' ' ' ' ...
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IDT77V011 & & ...
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IDT77V011 TxREF is a 8KHz reference clock output generated from REFCLK. REFCLK is a 8KHz reference clock input used to generate the TxREF clock signal. TxLED indicates if there is activity on the transmit UTOPIA 2 bus. This signal asserts ...
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IDT77V011 TCLK (output) TxADDR[4:0] 1B (output) TCLAV (input) TENB (output) TSOC (output) TxDATA[7:0] (output) TCLK (output) TxADDR[4:0] 04 (output) TCLAV (input) TENB (output) TSOC (output) TxDATA[7:0] 47 (output) Configuration 1 8001 0 Configuration 2 8002 [1:0] [6:2] Configuration 3 8003 ...
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IDT77V011 ' ...
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IDT77V011 DRxCLK (input/ output) DRxFRM (output) DRxDATA[3:0] 104 105 (output) Figure 8 Nibble Mode Back-to-Back Cell Transfer on Receive DPI Bus DTxCLK (output) DTxFRM (input) DTxDATA[3:0] (input) DTxCLK (output) DTxFRM (input) DTxDATA[3:0] 104 105 (input) Figure 10 Nibble Mode Back-to-Back ...
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IDT77V011 & ...
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IDT77V011 Pin Controls 801A (I) SYSCLK t t PALE (O) ALE PHYCS (O) (O) RD ...
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IDT77V011 ...
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IDT77V011 ...
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IDT77V011 (O) ADDR[11:0] SEL (O) (I/O) DATA[7:0] (O) WR/RW (O) RD/DS (I) RDY/DTACK (O) RD/DS (O) WR/RW (I) RDY/DTACK BMODE — MBUS[0] Tx TAG Size[0] MBUS[1] Tx TAG Size[1] MBUS[2] Tx TAG Size[2] MBUS[3] TxLOC MBUS[4] TxHEC MBUS[5] Rx TAG ...
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IDT77V011 MGMT[5] — PHYRST — PHYINT — MGMT[1] CS[0] MBUS[11:0] CS[12:1] MGMT[2] RD MGMT[3] WR MGMT[5] ALE MDATA[7:0] ADDR/DATA[7:0] PHYINT PHYINT PHYRST PHYRST BMODE BMODE MBUS[11:0] ADDR[11:0] MDATA[7:0] DATA[7:0] MGMT[1] SEL MGMT[2] RD/DS MGMT[3] WR/RW MGMT[4] RDY/DTACK PHYRST PHYRST PHYINT ...
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IDT77V011 ( ( ...
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IDT77V011 User Defined Reserved Discovery/Identify cell data Reserved In-Stream™ Subport In-Stream™ Cell Header Figure 16 EEPROM Memory Map 0xFFFFFF Reserved 0x008025 0x008024 77V011 Registers 0x008000 0x007FFF Reserved 0x000F00 0x000EFF PHY #30 Registers 0x000E00 0x000DFF PHY #29 Registers 0x000D00 0x000CFF PHY ...
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IDT77V011 & & ...
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IDT77V011 In-Stream™ Subport bits[4:0] of DPI Tx Subport Configuration Register Cell Interpreter Register Content Max Subports 0x1E Subport Width 0x5 Replace Subport 1 Bit Location 0x5 Byte Location 0x2 New Subport 0x1F x = Any valid subport address Byte 0 ...
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IDT77V011 ...
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IDT77V011 Configuration 2 8002 [6:2] Max Subports Subport 8013 [4:0] In-Stream™ Configuration 1 Subport [7:5] Tx Subport Width 0x0 - 0x7 Modify Tx 8014 [4:0] New Subport Subport 5 Replace Subport 0x0 - 0x7 Tx Subport Position 8015 [2:0] Tx ...
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IDT77V011 Configuration 1 8001 2 Rx Move PT/CLP Rx TAG 8005 [2:0] Rx Tag Size [2: Remove HEC 4 Rx TAG Location TAG byte 3 8016 [7:0] TAG [31:24] TAG byte 2 8017 [7:0] TAG [23:16] TAG byte ...
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IDT77V011 , ...
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IDT77V011 In-Stream™ Cell 800F [7:0] Header Byte 0 In-Stream™ Cell 8010 [7:0] Header Byte 1 In-Stream™ Cell 8011 [7:0] Header Byte 2 In-Stream™ Cell 8012 [7:0] Header Byte 3 Discover/ Identify 2 Reset 3 Read Registers 5 Write Registers 6 ...
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IDT77V011 UNI Cell Header (five byte field) Bit GFC VPI VCI VCI HEC Figure 21 Valid Header Formats for In-Stream Command Cell Transaction ID (two byte field) Bit Copied from ...
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IDT77V011 Device ID (seven byte field) Bit Not Used Not Used Not Used Not Used Not Used Not Used Figure 24 Valid Device ID Field Format for In-Stream ...
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IDT77V011 & & ...
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IDT77V011 UTOPIA Rx Cell 801B [7:0] Counter byte 3 UTOPIA Rx Cell 801C [7:0] Counter byte 2 UTOPIA Rx Cell 801D [7:0] Counter byte 1 UTOPIA Rx Cell 801E [7:0] Counter byte 0 UTOPIA Tx Cell 801F [7:0] Counter byte ...
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IDT77V011 t DPI DTxCLK/DRxCLK Cycle Time DCYC t DPI DTxCLK/DRxCLK High Time DCH t DPI DTxCLK/DRxCLK Low Time DCL t DTxFRM, DTxDATA to DTCLK Setup Time DTS t DTxFRM, DTxDATA to DTCLK Hold Time DTH t DRxCLK to DRxDATA(0-3), DRxFRM ...
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IDT77V011 t ADDR to RD/DS Falling Edge Setup Time ADRS t ADDR to RD/DS Rising Edge Hold Time ADRH t SEL to RD/DS Falling Edge Setup Time SELRS t SEL to RD/DS Rising Edge Hold Time SELRH t DATA Invalid/Tri-state ...
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IDT77V011 SYSCLK DRxCLK SYSCLK DTxCLK TCLK TxDATA(0-7), TENB, TSOC TCLAV RCLK RxDATA(0-7), RSOC, RCLAV DTxCLK DTxFRM, DTxDATA(0-3) tPDRxCLK Figure 30 System Clock to DPI Receive Clock Propagation Delay tPDTxCLK Figure 31 System Clock to DPI Transmit ...
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IDT77V011 DRxCLK DRxFRM, DRxDATA(0-3) SYSCLK SYSCLK SYSCLK EECS EECLK EEDO EEDI t PDRD Figure 35 DPI Receive Timing Waveform tPPHYR Figure 36 System ...
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IDT77V011 , ...
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IDT77V011 Mode Select 8006 [7:5] PHY Reset 8007 0 [7:1] Notification Mask 8008 0 1 [7:2] Status 8009 [7:3] Timeout Status 800A 0 1 [7:2] Dpi Size Defined by "Selects the size ...
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IDT77V011 Rx Out of Range 800B [4:0] Subport [7:5] Rx Out of Range 801C [7:0] Address Mask byte 2 Rx Out of Range 800D [7:0] Address Mask byte 1 Rx Out of Range 800E [7:0] Address Mask byte 0 In-Stream™ ...
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IDT77V011 Pin Controls 801A UTOPIA Rx Cell 801B [7:0] Counter byte 3 UTOPIA Rx Cell 801C [7:0] Counter byte 2 UTOPIA Rx Cell 801D [7:0] Counter byte 1 UTOPIA Rx Cell 801E ...
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IDT77V011 ...
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IDT77V011 ...