IDT77V011L155DA IDT, Integrated Device Technology Inc, IDT77V011L155DA Datasheet - Page 21

• Manufacturer Part Number: IDT77V011L155DA
• Description: INTERFACE DPI-UTOPIA 144-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77V011L155DA

• Interface: DPI, UTOPIA
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 144-TQFP, 144-VQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Applications: -
• Other names: 77V011L155DA

( ( 3
( ( 3 5 5 5 5 2 0 ,
( ( 3
( ( 3
initialization and Discovery/Identify commands. The data is broken up
into five fields.
placed in the In-Stream™ Cell Header and In-Stream™ Subport regis-
ters. Bytes [3:0] are used for the In-Stream™ Cell Header registers,
while byte [4] is used for the In-Stream™ Subport register. Bytes [7:5]
are not used at this time, while bytes [39:8] contain 32-bytes of data,
which is read when a Discovery/Identify command is encountered. Bytes
[40:127] are reserved and bytes [128:255] are user defined. The regis-
ters associated with the EEPROM are listed in the EEPROM Register
Table.
Select (EECS), Data Out (EEDOUT), and Data In (EEDIN).
write operation.
stored in the EEPROM to the In-Stream™ Cell Header and In-Stream™
Subport registers. Setting TxADDR[3] to a zero will select not to write
the five byte value, while setting it to a one will write the value to the
registers. The state of the TxADDR[3] signal, at reset, is stored in the Init
from EEPROM bit of the Mode Select register.
include Mux Select (EEPROM Mux Sel), Clock Out (EEPROM Clock
Out), Chip Select (EEPROM Chip Select), Data Out (EEPROM Out),
and Data In (EEPROM In).
connected to the internal logic, or to the EEPROM registers. When
connected to the Internal logic 32-bytes of data are read from the
EEPROM when a Discovery/Identify command is filtered. Controlling the
EEPROM from the registers enables the user the flexibility of reading
and writing the EEPROM at any time. Programming is accomplished
with In-Stream™ cells regardless of the method used to access the
EEPROM.
controlled by the registers. This register must be written to twice to
execute one EEPROM clock cycle. You must write to the clock register
to perform a read or write command.
face when being controlled by the EEPROM registers.
IDT77V011
The EEPROM interface is an optional device that can be used for
Bytes [4:0] contain a 5-byte value that can be read at reset and
Signals associated with this interface are Clock (EECLK), Chip
EECLK is generated from SYSCLK and is an output of the 77V011.
EECS is an active low chip select signal used to validate a read or
EEDOUT is a serial data output pin to the EEPROM.
EEIN is a serial input data pin from the EEPROM.
At reset TxADDR[3] selects whether or not to write the first five bytes
The EEPROM can be controlled with the EEPROM registers, which
EEPROM Mux Select indicates whether the EEPROM pins will be
EEPROM Clock Out is used to clock the EEPROM when it is being
EEPROM Chip Select validates transactions on the EEPROM inter-
EEPROM Out is a 1-bit register used to output data to the EEPROM.
EEPROM In is a 1-bit register used to input data from the EEPROM.
2 0 , Q W H U I D F H
2 0 ,
2 0 ,
Q W H U I D F H
Q W H U I D F H
Q W H U I D F H
21 of 43
7 7 7 7 U U U U D Q V P L W &
up to five bits wide and be located anywhere in the first four bytes of the
ATM cell, or first eight bytes of the cell if a four byte pre-pended TAG is
being used. It can start in any bit location of a byte and can span over
the byte boundary.
route the cell. Normal cells have a PHY subport value from zero to the
value stored in Max Subports bits of the Configuration 2 register. The
Max Subport can be any value between zero and 30, as the UTOPIA 2
specification allows a total of 31 PHY ports to be connected to a
UTOPIA 2 interface. The cell will be dropped if a subport greater than
the Max Subports value is used.
value with the value contained in the New Subport bits of the Modify Tx
Subport register. Overwriting is determined by the Replace Subport bit
of the Modify Tx Subport register. Only the data cells are affected when
the 77V011 is configured to overwrite the subport field. The subport field
of In-Stream™ cells are not altered.
what byte of the header the subport field starts in. Valid values are zero
to three without using a TAG, and zero to seven when using a TAG. The
subport field can start in any byte location of the header. This value is
programmed at reset with TxADDR[2:0] pins. The 77V011 will concate-
nate the transmit subport field if any part of the subport field extends into
the payload area of the cell. This is to ensure that the payload will not be
altered.
tion. This value indicates what bit in the byte the subport MSB is located
in. A value of zero means that bit zero of the selected byte is MSB, bit 7
of the next byte is MSB-1, etc.... The subport can start on any bit of a
byte and span multiple bytes.
programmed in the Tx Subport Width field bits of the Subport Configura-
tion 1 register. The subport width can be any value between one and
five, with the default value being five.
to zero. When this is done, the cell will be passed to the transmit
UTOPIA bus unchanged, and the polled address will be 0x0. This mode
of operation is intended for system configurations with a single PHY
device.
Transmit Cell Routing Register Table.
A subport address is used to select a PHY port. The address can be
The 77V011 uses the transmit subport field in determining how to
Once the subport field is read the 77V011 can replace the subport
The Tx Byte Location bits of the Tx Subport Position register indicate
Bits [5:3] of the Tx Subport Position register contain the Tx Bit Loca-
The number of bits to be used for the transmit subport field is
A special mode of operation occurs when the Tx Subport Width is set
Registers associated with the transmit cell routing are defined in the
D Q V P L W & H H H H O O O O O O O O 5 5 5 5 R X R X R X R X W W W W L Q J
D Q V P L W &
D Q V P L W &
L Q J
L Q J
L Q J
March 15, 2001