IDT77V011L155DA IDT, Integrated Device Technology Inc, IDT77V011L155DA Datasheet - Page 34

• Manufacturer Part Number: IDT77V011L155DA
• Description: INTERFACE DPI-UTOPIA 144-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77V011L155DA

• Interface: DPI, UTOPIA
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 144-TQFP, 144-VQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Applications: -
• Other names: 77V011L155DA

IDT77V011
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
DCYC
DCH
DCL
DTS
DTH
PDRD
ALPW
ALR
ALW
RDPW
AAL
ALA
DRS
DRH
DWS
DWH
WRPW
PINTS
PINTH
AW
PALE
PPHY
PPHYR
PRCLK
PTCLK
PDRxCLK
PDTxCLK
PRLED
PTLED
PCNTA
PCNTB
RSTW
ECYC
PECLK
SEDI
HEDI
Table 24 AC Electrical Characteristics (Industrial: Vcc = 5V ± 10%, TA = -40 C the 85 C (Part 2 of 3)
DPI DTxCLK/DRxCLK Cycle Time
DPI DTxCLK/DRxCLK High Time
DPI DTxCLK/DRxCLK Low Time
DTxFRM, DTxDATA to DTCLK Setup Time
DTxFRM, DTxDATA to DTCLK Hold Time
DRxCLK to DRxDATA(0-3), DRxFRM Propagation Delay
ALE Pulse Width
System Clock to READ Low Propagation Delay
System Clock to WRITE Low Propagation Delay
Read Pulse Width
Address to ALE Falling Edge Setup Time
Address to ALE Falling Edge Hold Time
Data to rising edge of READ Setup Time
Data to rising edge of READ Hold Time
Data to rising edge of WRITE Setup Time
Data to rising edge of WRITE Hold Time
Write Pulse Width
System Clock to PHYINT Setup Time
System Clock to PHYINT Hold Time
ALE falling edge to WR falling edge
ALE to System Clock Propagation Delay
System Clock to PHYCS Propagation Delay
System Clock to PHYRST Propagation Delay
System Clock to Utopia Receive Clock Propagation Delay
System Clock to Utopia Transmit Clock Propagation Delay
System Clock to DPI Receive Clock Propagation Delay
System Clock to DPI Transmit Clock Propagation Delay
System Clock to RxLED Propagation delay
System Clock to TxLED Propagation delay
System Clock to CONT_A Propagation delay
System Clock to CONT_B Propagation delay
SYSRST pulse width
EECLK Cycle Time
SYSCLK to EECLK, EECS, EEDOUT Propagation Delay
SYSCLK to EEDIN Setup Time
SYSCLK to EEDIN Hold Time
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20
8
8
4
2
—
20
—
—
80
20
10
5
1
5
1
40
10
1
25
—
—
—
—
—
—
—
—
—
—
—
100
1000
—
—
2
—
—
—
—
—
10
—
20
20
—
—
—
—
—
—
—
—
—
—
—
20
20
20
20
20
20
20
20
20
20
20
—
—
20
10
—
March 15, 2001
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns