IDT77V011L155DA IDT, Integrated Device Technology Inc, IDT77V011L155DA Datasheet - Page 39

• Manufacturer Part Number: IDT77V011L155DA
• Description: INTERFACE DPI-UTOPIA 144-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77V011L155DA

• Interface: DPI, UTOPIA
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 144-TQFP, 144-VQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Applications: -
• Other names: 77V011L155DA

Mode Select
PHY Reset
Notification Mask
Status
Timeout Status
IDT77V011
8006
8007
8008
8009
800A
0
1
2
3
4
[7:5]
0
[7:1]
0
1
[7:2]
0
1
2
[7:3]
0
1
[7:2]
Dpi Size
Dpi Mode
UTOPIA 2 Size
UTOPIA Man-
agement Mode
Init from
EEPROM
Not Used
PHY Reset
Not Used
PHY Interrupt
Mask
Rx Address Error 0
Not Used
PHY Interrupt
Address Range
Error
Tx Cell Dropped 0
Not Used
PHY Interrupt
Status
Address Error
Status
Not Used
Table 25 Internal Register Map (Part 2 of 4)
Defined by
Defined by
pin
pin
Defined by
pin
Defined by
pin
Defined by
pin
0
0
0
0
0
0
39 of 43
"Selects the size of the DPI Tx and Rx data bus. "0" 4-bit DPI Tx and Rx
data bus, "1" 8-bit DPI Tx and Rx data bus."
"Selects DRxCLK direction. "0" switch mode (output), "1" normal mode
(input)."
"Selects the size of the UTOPIA 2 Tx and Rx data bus. "0" 8-bit UTOPIA 2
Tx and Rx data bus, "1" 16-bit UTOPIA 2 Tx and Rx data bus."
"Selects type of management interface to use. "0" Utility bus style, "1" UTO-
PIA 2 management style."
"Five byte write from EEPROM to In-Stream™ Cell Header and In-Stream™
Subport registers at reset. "0" do not write five byte value, "1" write five byte
value to registers."
"PHY Reset. "0" do not reset the PHY, "1" reset the PHY(PHYRST signal
will be asserted low for at least 16 SYSCLK cycles."
"Mask interrupt notification. "0" no Event Notification cell will be generated
when a PHY interrupt occurs, "1" generate Event Notification cell when a
PHY interrupt occurs."
"Mask Address Range Error notification. "0" no Event Notification cell will be
generated when a Rx Out of Range Address Error occurs, "1" generate
Event Notification cell when a Rx Out of Range Address Error occurs."
"When a PHY interrupt occurs on the external PHY interrupt pin this bit will
be set high. "0" no interrupt detected, "1" PHY interrupt detected."
"Address Range Error indication when an Address Range Error occurs. "0"
no Address Range Error detected, "1" Address Range Error has been
detected."
"Indicates if any cells have been dropped at the transmit UTOPIA interface.
This is a status indicator for the Stall Tx bit of the Configuration 2 register "0"
no cells have been dropped, "1" a cell was dropped because the PHY did
not respond."
"Indicates that a PHY interrupt occurred more than 25ms ago, and the PHY
Interrupt bit of the Status register has not been cleared. This bit will return to
zero once the interrupt is cleared. "0" no PHY interrupt detected, "1" inter-
rupt occurred more than 25ms ago and has not been cleared."
"Indicates that a Address Error occurred more than 25ms ago, and Address
Range Error bit of the Status register has not been cleared. This bit will
return to zero once the interrupt is cleared. "0" no Address Range Errors
detected, "1" Address Range Error occurred more than 25ms ago and has
not been cleared."
March 15, 2001