MCZ33989EGR2 Freescale Semiconductor, MCZ33989EGR2 Datasheet - Page 33

• Manufacturer Part Number: MCZ33989EGR2
• Description: IC SYSTEM BASIS CHIP CAN 28-SOIC
• Manufacturer: Freescale Semiconductor

Specifications of MCZ33989EGR2

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 28-SOIC (7.5mm Width)
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

High-Speed CAN Transceiver Modes
Normal or Sleep modes. Please see
defines the slew rate when the CAN module is in Normal
Table 16. CAN High-Speed Transceiver Modes
Table 17. CAN Status Bits
set to 1 when the CAN interface is programmed into CAN
NORMAL for the first time after V2 turn ON. To clear the CUR
bit, follow this procedure:
• Turn V2 ON (SBC in Normal mode and V2 above V2
Table 18. IOR Register
Table 19. IOR Control Bits
condition, it can be turned ON again by setting the
Analog Integrated Circuit Device Data
Freescale Semiconductor
The mode bit (D0) controls the state of the CAN module,
Error bits are latched in the CAN registers. Bit (1) CUR is
threshold) the CAN interface must be set into CAN Sleep
When HS1 is turned OFF due to an over temperature
Reset Condition
Reset Value
SC1
Status Bits
0
0
1
1
x
x
$011B
CANWU
THERM
CUR(1)
IOR
HS1ON
TXF
0
1
SC0
0
1
0
1
1
0
CAN Wake-up Occurred
Permanent Dominant TX
CAN Transceiver in Current Limitation
CAN Transceiver in Thermal Shutdown
W
R
HS1 OFF, in Normal and Standby Modes
HS1 ON, in Normal and Standby Modes
Table
MODE
0
0
0
0
1
1
V2LOW
16. SC0 bit (D1)
D3
—
—
—
CAN Normal, Slew Rate 0
CAN Normal, Slew Rate 1
CAN Normal, Slew Rate 2
CAN Normal, Slew Rate 3
CAN Sleep and CAN Wake-up Disable
CAN Sleep and CAN Wake-up Enable
HS1ON
HS1OT
POR
mode, and controls the wake-up option (wake-up enable or
disable) when the CAN module is in Sleep mode. CAN
module modes (Normal and Sleep) are independent of the
SBC modes. Please see
• Return to CAN NORMAL
Input/Output Control Register (IOR)
Standby modes, while
appropriate control bit to 1. Error bits are latched in the Input/
Output Registers (IOR). Please see
D2
0
Table 18
Description
HS1 State
provides data about HS1 control in Normal and
CAN Mode
VSUPLOW
Table 19
LOGIC COMMANDS AND REGISTERS
D1
—
—
—
Table
FUNCTIONAL DEVICE OPERATION
17.
provides control bit data.
Table
20.
DEBUG
D0
—
—
—
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