MT41J256M4JP-125:G Micron Technology Inc, MT41J256M4JP-125:G Datasheet - Page 95

• Manufacturer Part Number: MT41J256M4JP-125:G
• Description: IC DDR3 SDRAM 1GBIT 78FBGA
• Manufacturer: Micron Technology Inc
• Series: -r

Specifications of MT41J256M4JP-125:G

• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 1G (256M x 4)
• Speed: 800MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 78-TFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

REFRESH
Figure 43: Refresh Mode
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_4.fm - Rev. F 11/08 EN
DQS, DQS# 4
Command
Address
BA[2:0]
DM 4
DQ 4
CK#
CKE
A10
CK
NOP 1
T0
Notes:
One bank
All banks
Bank(s) 3
there is no open row in that bank (idle state) or if the previously open row is already in
the process of precharging. However, the precharge period is determined by the last
PRECHARGE command issued to the bank.
REFRESH is used during normal operation of the DRAM and is analogous to CAS#-
before-RAS# (CBR) refresh or auto refresh. This command is nonpersistent, so it must be
issued each time a refresh is required. The addressing is generated by the internal refresh
controller. This makes the address bits a “Don’t Care” during a REFRESH command. The
DRAM requires REFRESH cycles at an average interval of 7.8µs (maximum when T
85°C or 3.9µs MAX when T
switching between tasks, some flexibility in the absolute refresh interval is provided. A
maximum of eight REFRESH commands can be posted to any given DRAM, meaning
that the maximum absolute interval between any REFRESH command and the next
REFRESH command is nine times the maximum average interval refresh rate. The
REFRESH period begins when the REFRESH command is registered and ends
(MIN) later.
1. NOP commands are shown for ease of illustration; other valid commands may be possible at
2. The second REFRESH is not required but depicts two back-to-back REFRESH commands.
3. “Don’t Care” if A10 is HIGH at this point; however, A10 must be HIGH if more than one
4. For operations shown, DM, DQ, and DQS signals are all “Don’t Care”/High-Z.
PRE
T1
these times. CKE must be active during the PRECHARGE, ACTIVATE, and REFRESH com-
mands, but may be inactive at other times (see "Power-Down Mode" on page 151).
bank is active (must precharge all active banks).
t CK
NOP 1
T2
t CH
t RP
t CL
NOP 1
T3
C
≤ 95°C). To allow for improved efficiency in scheduling and
REF
T4
95
t RFC (MIN)
Valid 1
NOP 1
Ta0
Micron Technology, Inc., reserves the right to change products or specifications without notice.
REF 2
Ta1
1Gb: x4, x8, x16 DDR3 SDRAM
Valid 1
NOP 1
Tb0
Indicates A Break in
Time Scale
©2006 Micron Technology, Inc. All rights reserved.
t RFC 2
Valid 1
NOP 1
Tb1
Don’t Care
Commands
Tb2
ACT
RA
RA
BA
t
RFC
C
≤