PEB22504HT-V11 Infineon Technologies, PEB22504HT-V11 Datasheet - Page 87

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PEB22504HT-V11

Manufacturer Part Number
PEB22504HT-V11
Description
IC INTERFACE QUAD 100-TQFP
Manufacturer
Infineon Technologies
Datasheet

Specifications of PEB22504HT-V11

Applications
*
Interface
*
Voltage - Supply
*
Package / Case
100-LFQFP
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PEB22504HT-V11
PEB22504HT-V11IN

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PEB22504HT-V11
Manufacturer:
Infineon Technologies
Quantity:
10 000
Flexible Clock Mode Settings
If flexible master clock mode is used (VFREQ_EN = 1), the according register settings
can be calculated as follows (a windows-based program for automatic calculation is
available, see
table below.
1. PLL_M and PLL_N must satisfy the equations:
a. 1.5 MHz
b. If a. is not possible, set MCLK_LOW and fulfill
1.02 MHz
c. 65 MHz
(as high as possible within this range)
2. Selection of best dividing mode:
f
f
If the target frequency cannot be reached exactly, the dividing mode has to be selected
to reach a frequency that is as near as possible to the target frequency.
3. Calculation of correction value (frequency mismatch correction)
PHD_E1 = 6
PHD_T1 = 6
The result of these equations is between -2048 and +2047. Negative values are
represented in 2s-complement format (e.g., -2000
Table 15
Data Sheet
outE1
outT1
f
MCLK
10.000
12.352
1.544
2.048
8.192
= ( f
= ( f
[MHz]
MCLK
MCLK
f
f
MCLK
f
MCLK
MCLK
Clock Mode Register Settings for E1 or T1/J1
Chapter 9.2
4096
4096
(2 PLL_N+2)/(PLL_M+1) )/DIV_T1 (target T1: 12.352 MHz)
(2 PLL_N+2)/(PLL_M+1) )/DIV_E1 (target E1: 16.384 MHz)
/(PLL_M + 1)
GCM1
/(PLL_M + 1)
F0
00
00
90
F0
(2 PLL_N + 2)/(PLL_M + 1)
H
H
H
H
H
[DIV_T1 - (2 PLL_N+2)/(PLL_M+1)
[DIV_E1 - (2 PLL_N+2)/(PLL_M+1)
on
page
GCM2
51
58
58
51
51
1.5 MHz
H
H
H
H
H
2.048 MHz
119). For some of the standard frequencies see the
GCM3
87
D2
D2
00
81
00
H
H
H
H
H
D
69.7 MHz
= 830
GCM4
C2
C2
8F
80
80
H
H
H
H
H
H
; +2000
(f
(f
MCLK
MCLK
Register Description
GCM5
D
/12.352 MHz)]
00
00
03
04
07
/16.384 MHz)]
= 7D0
H
H
H
H
H
QuadLIU V1.1
PEB 22504
H
).
GCM6
15
10
10
10
15
2001-02
H
H
H
H
H

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