PEB22504HT-V11 Infineon Technologies, PEB22504HT-V11 Datasheet - Page 93

• Manufacturer Part Number: PEB22504HT-V11
• Description: IC INTERFACE QUAD 100-TQFP
• Manufacturer: Infineon Technologies

Specifications of PEB22504HT-V11

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 100-LFQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB22504HT-V11; PEB22504HT-V11IN

Interrupt Status Register 0 (Read)
Addresses: 17
Value after reset: 00
ISR0
All bits are reset when ISR0 is read.
If bit LIM4.VIS is set, interrupt statuses in ISR0 may be flagged although they are
masked via register IMR0. However, these masked interrupt statuses neither generate a
signal on INT, nor are they visible in register CIS.
LLBSC
XLSC
PRBSSC
SLN
Data Sheet
LLBSC
7
H
, 37
Line Loop Back Status Change
Depending on bit LIM0.ARL the interrupt source is changed.
LIM0.ARL = 0 : This bit is set if the LLB activate signal or the LLB
deactivate signal is detected over a period of 25 ms/33.16 ms (E1/T1)
with a bit error rate less than 10
The LLBSC bit is also set if the current detection status is left, i.e., if
the bit error rate exceeds 10
LIM0.ARL = 1 : This bit is set high with any change of state of bit
LSR0.RLS.
Transmit Line Status Change
XLSC is set with the rising edge of the bit LSR1.XLO or with any
change of bit LSR1.XLS.
The actual status of the transmit line monitor can be read from
LSR1.XLS and LSR1.XLO.
PRBS Status Change
This bit is set with any change of state of the PRBS synchronizer. The
current status of the PRBS synchronizer is indicated in LSR0.PRBSS.
Slip Negative
The frequency of the receive route clock is greater than the frequency
of the receive framer interface working clock based on 2.048 MHz
(E1)/1.544 MHz (T1/J1). Data is skipped. SLN is also set during alarm
simulation.
XLSC PRBSSC
H
H
, 57
H
, 77
H
SLN
93
SLP
-2
.
-2
.
PDENI
AIS
Register Description
QuadLIU V1.1
LOS
0
PEB 22504
2001-02