CY8CKIT-050 Cypress Semiconductor Corp, CY8CKIT-050 Datasheet - Page 23

• Manufacturer Part Number: CY8CKIT-050
• Description: DEV KIT PSOC 5 CY8C55
• Manufacturer: Cypress Semiconductor Corp
• Series: PSoC®5r
• Type: MCUr

Specifications of CY8CKIT-050

• Design Resources: PSoC 5 Dev Kit Schematic CY8CKIT-050 PCBA BOM CY8CKIT-50 Gerber File
• Contents: Board, Cable, CD, Display, Documentation
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: CY8C55
• Other names: 428-3110

Table 6-2. Power Modes
Table 6-3. Power Modes Wakeup Time and Power Consumption
Figure 6-5. Power Mode Transitions
Document Number: 001-66235 Rev. *A
Active
Alternate
Active
Sleep
Hibernate
Note
Power Modes
Active
Alternate
Active
Sleep
Hibernate
7. Bus clock off. Execute from CPU instruction buffer at 6 MHz. See
Modes
Sleep
Manual
20 µs typ
Wakeup
<100 µs
Time
Alternate
Primary mode of operation, all
peripherals available (program-
mable)
Similar to Active mode, and is
typically configured to have
fewer peripherals active to
reduce power. One possible
configuration is to use the UDBs
for processing, with the CPU
turned off
All subsystems automatically
disabled
All subsystems automatically
disabled
Lowest power consuming mode
with all peripherals and internal
regulators disabled, except
hibernate regulator is enabled
Configuration and memory
contents retained
–
–
Active
Active
Sleep
Current
5 mA
(Typ)
3 µA
1 µA
Description
–
[7]
Execution
defined
Code
User
Yes
No
No
Hibernate
PRELIMINARY
Resources
Wakeup, reset,
manual register
entry
Manual register
entry
Manual register
entry
Manual register
entry
Entry Condition Wakeup Source
Digital
None
None
All
All
Table 11-2 on page
Resources
Analog
None
None
All
All
Any interrupt
Any interrupt
PICU, RTC,
CTW, LVD
PICU
6.2.1.1 Active Mode
Active mode is the primary operating mode of the device. When
in active mode, the active configuration template bits control
which available resources are enabled or disabled. When a
resource is disabled, the digital clocks are gated, analog bias
currents are disabled, and leakage currents are reduced as
appropriate. User firmware can dynamically control subsystem
power by setting and clearing bits in the active configuration
template. The CPU can disable itself, in which case the CPU is
automatically reenabled at the next wakeup event.
When a wakeup event occurs, the global mode is always
returned to active, and the CPU is automatically enabled,
regardless of its template settings. Active mode is the default
global power mode upon boot.
60.
PSoC
Clock Sources
ILO/kHzECO
Available
®
None
All
All
5: CY8C55 Family Datasheet
Any
(programmable)
Any
(programmable)
ILO/kHzECO
Active Clocks
PICU, RTC, CTW,
Wakeup Sources Reset Sources
PICU
LVD
–
–
All regulators available.
Digital and analog
regulators can be disabled
if external regulation used.
All regulators available.
Digital and analog
regulators can be disabled
if external regulation used.
Both digital and analog
regulators buzzed.
Digital and analog
regulators can be disabled
if external regulation used.
Only hibernate regulator
active.
Regulator
Page 23 of 114
XRES, LVD,
XRES
WDR,
All
All
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