CY8CKIT-050 Cypress Semiconductor Corp, CY8CKIT-050 Datasheet - Page 59

• Manufacturer Part Number: CY8CKIT-050
• Description: DEV KIT PSOC 5 CY8C55
• Manufacturer: Cypress Semiconductor Corp
• Series: PSoC®5r
• Type: MCUr

Specifications of CY8CKIT-050

• Design Resources: PSoC 5 Dev Kit Schematic CY8CKIT-050 PCBA BOM CY8CKIT-50 Gerber File
• Contents: Board, Cable, CD, Display, Documentation
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: CY8C55
• Other names: 428-3110

11. Electrical Specifications
Specifications are valid for -40 °C ≤ T
where noted. The unique flexibility of the PSoC UDBs and analog blocks enable many functions to be implemented in PSoC Creator
components, see the component datasheets for full AC/DC specifications of individual functions. See the
section on page 32 for further explanation of PSoC Creator components.
11.1 Absolute Maximum Ratings
Table 11-1. Absolute Maximum Ratings DC Specifications
Note Usage above the absolute maximum conditions listed in
maximum conditions for extended periods of time may affect device reliability. When used below maximum conditions but above
normal operating conditions the device may not operate to specification.
Document Number: 001-66235 Rev. *A
T
V
V
V
V
V
V
V
V
V
V
Ivddio
Vextref
LU
ESD
ESD
Notes
11. The V
12. Meets or exceeds JEDEC Spec EIA/JESD78 IC Latch-up Test.
STG
DDA
DDD
DDIO
CCA
CCD
SSA
GPIO
SIO
IND
BAT
Parameter
HBM
CDM
[11]
DDIO
supply voltage must be greater than the maximum analog voltage on the associated GPIO pins. Maximum analog voltage on GPIO pin ≤ V
Storage temperature
Analog supply voltage relative to
V
Digital supply voltage relative to
V
I/O supply voltage relative to V
Direct analog core voltage input
Direct digital core voltage input
Analog ground voltage
DC input voltage on GPIO
DC input voltage on SIO
Voltage at boost converter input
Boost converter supply
Current per V
ADC external reference inputs
Latch up current
Electrostatic discharge voltage
ESD voltage
SSA
SSD
Description
DDIO
[12]
supply pin
A
≤ 85 °C and T
PRELIMINARY
SSD
J
≤ 100 °C, except where noted. Specifications are valid for 2.7 V to 5.5 V, except
Recommended storage temper-
ature is +25 °C ±25 °C. Extended
duration storage temperatures
above 85 °C degrade reliability.
Includes signals sourced by V
and routed internal to the pin.
Output disabled
Output enabled
Pins P0[3], P3[2]
Human body model
Charge device model
Table 11-1
Conditions
PSoC
may cause permanent damage to the device. Exposure to
®
DDA
5: CY8C55 Family Datasheet
V
V
V
V
V
SSD
SSD
SSD
SSD
SSD
–140
–0.5
–0.5
–0.5
–0.5
–0.5
Min
–55
500
500
0.5
–
–
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
Typ
“Example Peripherals”
25
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
V
V
DDIO
Max
1.95
1.95
SSD
Page 59 of 114
100
140
0.5
0.5
5.5
5.5
20
6
6
6
7
6
2
–
–
+
+
DDIO
Units
≤ V
mA
mA
°C
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DDA
.
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