OM13001,598 NXP Semiconductors, OM13001,598 Datasheet - Page 36
![EA LPC177X/8X EVAL BOARD](/photos/40/8/400885/om13001_598_sml.jpg)
OM13001,598
Manufacturer Part Number
OM13001,598
Description
EA LPC177X/8X EVAL BOARD
Manufacturer
NXP Semiconductors
Series
-r
Type
MCUr
Specifications of OM13001,598
Contents
Board, Cable, Headphones, Registration Card
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With/related Products
LPC1788
Other names
568-6707
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NXP Semiconductors
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10] 5 V tolerant pad with 5 ns glitch filter providing digital I/O functions with TTL levels and hysteresis.
[11] <tbd>
[12] 5 V tolerant pad with 20 ns glitch filter providing digital I/O function with TTL levels and hysteresis.
[13] <tbd>
[14] Pad provides special analog functionality.
[15] If the RTC is not used, these pins can be left floating.
[16] When the main oscillator is not used, connect XTAL1 and XTAL2 as follows: XTAL1 can be left floating or can be grounded (grounding
Table 4.
Not all functions are available on all parts. See
LPC178X_7X
Objective data sheet
Ball
Row A
1
5
9
13
17
Row B
1
5
9
13
17
Row C
1
5
9
13
17
Row D
1
5
I = Input; O = Output; G = Ground; S = Supply.
5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis.
<tbd>
5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis and analog input. When configured as a ADC input, digital
section of the pad is disabled.
<tbd>
5 V tolerant pad providing digital I/O with TTL levels and hysteresis and analog output function. When configured as the DAC output,
digital section of the pad is disabled.
Open-drain 5 V tolerant digital I/O pad, compatible with I
functionality. When power is switched off, this pin connected to the I
configuration applies to all functions on this pin.
Not 5 V tolerant. Pad provides digital I/O and USB functions. It is designed in accordance with the USB specification, revision 2.0
(Full-speed and Low-speed mode only).
is preferred to reduce susceptibility to noise). XTAL2 should be left floating.
Symbol
P3[27]
P1[4]
P1[17]
P3[20]
P1[5]
P3[2]
P1[1]
P4[25]
V
P2[0]
P3[13]
P3[9]
V
P0[7]
V
JTAG_TRST
P3[11]
DD(3V3)
DD(3V3)
DD(3V3
Pin allocation table TFBGA208
)
Ball Symbol
2
6
10
14
2
6
10
14
2
6
10
14
2
6
V
P1[9]
P1[3]
P1[11]
-
P3[10]
V
P4[29]
P3[19]
-
JTAG_TDI
P3[22]
P3[21]
P0[9]
-
P3[28]
P0[3]
SS
SS
All information provided in this document is subject to legal disclaimers.
Table 2
Rev. 2 — 27 May 2011
2
and
C-bus 400 kHz specification. It requires an external pull-up to provide output
Table 7
Ball
3
7
11
15
3
7
11
15
3
7
11
15
3
7
2
C-bus is floating and does not disturb the I
(EMC pins).
Symbol
P1[0]
P1[14]
P4[15]
P0[8]
-
P3[1]
P4[30]
P1[6]
P4[14]
-
P5[4]
P1[8]
P4[28]
P3[18]
-
JTAG_TDO (SWO)
V
DD(3V3)
32-bit ARM Cortex-M3 microcontroller
Ball
4
8
12
16
4
8
12
16
4
8
12
16
4
8
LPC178x/7x
Symbol
P4[31]
P1[15]
V
P1[12]
-
P3[0]
P4[24]
P0[4]
P4[13]
-
P0[2]
P1[10]
P0[5]
P4[12]
-
P3[12]
P3[8]
SS
2
C lines. Open-drain
© NXP B.V. 2011. All rights reserved.
36 of 117
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