TS68C429AMFA E2V, TS68C429AMFA Datasheet - Page 15

• Manufacturer Part Number: TS68C429AMFA
• Manufacturer: E2V

Specifications of TS68C429AMFA

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: -55C to 125C
• Operating Temperature Classification: Military
• Mounting: Surface Mount
• Pin Count: 132
• Lead Free Status / Rohs Status: Compliant

8.1.3
e2v semiconductors SAS 2008
Description
Figure 8-1.
Each channel has a test mode in which the input signals (RXiH, RXiL), are internally connected to the
third Transmit Channel Lines. This selection is done by programming the Test bit in the receiver control
register (see
the same manner in the two modes. The receiver channel block diagram is given in
ARINC signals being asynchronous, the RCU first rebuilds the received clock in order to transfer the
data within the shift-register and when the Gap-controller has detected the end of the message, tests the
message validity according to the criteria listed hereafter.
To detect the end of the message, the Gap-Controller waits for a Gap after the last received bit. To do
so, at each CLK ARINC cycle, a counter is incremented and compared to the content of the Gap-Regis-
ter which has the user programmed value. If both values are equal, the counter is stopped and an
internal end of message signal is generated. This counter is reseted on the falling edge of the rebuilt
clock.
When the end of message is detected, the TS68C429A verifies the following points:
If not, reception of a new message is enabled, see Note.
If only the message parity is incorrect, an interrupt can be generated (see
17).
The Buffer is seen as two 16-bit word registers, the Most Significant Word of the message (MSW) is con-
tained in the lower address, the Less Significant Word of the message (LSW) is contained in the upper
address. The MSW should be read first because reading the LSW will release the buffer and allow trans-
fer of a new message from the Shift-register.
• the number of received bits must be 32,
• if requested the message parity (see
• the message label must be equal to one of the label stored in the Label Control Matrix,
• the Buffer is empty (that is: the last message has been read). The corresponding bit in the Status-
• when all four conditions are met, the message is transferred from the Shift-register to the Buffer and
of the message,
register (see logical interface unit), has been cleared,
the corresponding bit is set in the Status-register. If the interrupt mode is enabled (see
Circuit Control” on page
Figure 8-2
“Register Description” on page
shows the gap detection principle.
24) the IRQRX line is activated.
“Register Description” on page
17) except this difference, the TS68C429A behaves exactly
17) is compared to the parity bit
“Register Description” on page
0848E–HIREL–02/08
Figure
TS68C429A
“General
8-2.
15