TS68C429AMFA E2V, TS68C429AMFA Datasheet - Page 24

• Manufacturer Part Number: TS68C429AMFA
• Manufacturer: E2V

Specifications of TS68C429AMFA

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: -55C to 125C
• Operating Temperature Classification: Military
• Mounting: Surface Mount
• Pin Count: 132
• Lead Free Status / Rohs Status: Compliant

Table 9-1.
9.3
9.3.1
24
Bit
Bit 15
Bit 14
Bit 13 to 12
Bus 11
Bit 10
Bit 9 to 5
Bit 4
Bit 3 to 0
0848E–HIREL–02/08
General Circuit Control
Logical Control Unit (LCU)
Transmission Control Register Description
Function
Enable transmission
Test (only 3rd channel)
Not used
Parity control
Parity control
Transmission gap
Reset FIFO
Number of msg
•
The FIFO is seen as two 16-bit words. The Most Significant Word (MSW) must be written first. The Least
Significant Word (LSW) write increments the FIFO counter.
Before any write, the user should verify that the FIFO is not full. If the FIFO is full, any write to the FIFO
will be lost.
The LCU mainly distributes the clocks and reset within the MRT. The reset signal, active low is an asyn-
chronous signal. When it occurs, all registers are reset to zero except the Label-Control-Matrix which is
not initialized and the Status-Register which is set to FC00 (hex). Reset duration must be greater than 4
clk-cyc periods.
The LCU contains the Status-register. This read/write register indicates the state of the internal opera-
tions. It is also the image of the pending interrupts if they are not masked. Clearing a bit “RX-Channel-i”
will cancel the received message and release the Message-buffer for reception of a new message. The
“End of TX on channel-i” Is set only when the involved channel FIFO is empty. The format of the Status-
Register is given below.
FIFO
Comments
- 0: channel out of service (stops on going transmission)
- 1: channel in service
- 1 to 0: transition is not allowed at the same time as an 1 to 0 transition of the bit 4
- when the transmitter FIFO is empty and when no transmission is on going, the first
write access to the FIFO has to be preceded by the following sequence: reset to 0
and then set to 1
0: normal operating
1: test, output are only driven on internal lines for input testing
0: even parity calculation
1: odd parity calculation
0: parity disable, Bit 32 of the message stays unchanged
1: parity enable. Bit 32 of the message will be forced by parity control
“transmission gap” which is the delay between two 32-bit ARINC messages (in
ARINC bit)
- write a 0 in this bit reset the FIFO counter
- this bit must be set to 1 before any write in the transmit buffer.
- 1 to 0: transition is not allowed at the same time as an 1 to 0 transition of the bit 15
these four bits indicate the available space within the FIFO
e2v semiconductors SAS 2008
TS68C429A