AM79C971AKC\WQOCML AMD (ADVANCED MICRO DEVICES), AM79C971AKC\WQOCML Datasheet - Page 128

• Manufacturer Part Number: AM79C971AKC\WQOCML
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C971AKC\WQOCML

• Operating Supply Voltage (typ): 3.3/5V
• Operating Temperature Classification: Commercial
• Package Type: PQFP
• Mounting: Surface Mount
• Pin Count: 160
• Lead Free Status / Rohs Status: Not Compliant

6
5
4
128
MAPINTE
MCCINT
MCCINTE
When MAPINT is set to 1, INTA is
asserted if the enable bit MAP-
INTE is set to 1.
Read/Write accessible always.
MAPINT is cleared by the host by
writing a 1. Writing a 0 has no ef-
fect. MAPINT is cleared by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
MAPINTE is set, the MAPINT bit
will be able to set the INTR bit.
Read/Write accessible always.
MAPINTE
H_RESET and is not affected by
S_RESET or setting the STOP bit
Complete Interrupt. The MII Man-
agement Command Complete In-
terrupt is set by the Am79C971
controller when a read or write
operation to the MII Data Port
(BCR34) is complete.
When MCCINT is set to 1, INTA
is asserted if the enable bit MC-
CINTE is set to 1.
Read/Write accessible always.
MCCINT is cleared by the host by
writing a 1. Writing a 0 has no ef-
fect. MCCINT is cleared by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
Complete Interrupt Enable. If
MCCINTE is set to 1, the MC-
CINT bit will be able to set the
INTR bit when the host reads or
writes to the MII Data Port
(BCR34) only. Internal MII Man-
agement Commands will not gen-
erate an interrupt. For instance
Auto-Poll state machine generat-
ed MII management frames will
not generate an interrupt upon
completion unless there is a com-
pare error which get reported
through the MAPINT (CSR7, bit
6) interrupt or the MCCIINTE is
set to 1.
MII Auto-Poll Interrupt Enable. If
MII
MII
Management
Management
is
set
to
Command
Command
0
Am79C971
by
3
2
MCCIINT
MCCIINTE MII
Read/Write accessible always.
MCCINTE
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
When MCCIINT is set to 1, INTA
is asserted if the enable bit MC-
CINTE is set to 1.
Read/Write accessible always.
MCCIINT is cleared by the host
by writing a 1. Writing a 0 has no
effect. MCCIINT is cleared by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
Read/Write accessible always.
MCCIINTE
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
MII
Complete Internal Interrupt. The
MII
Complete Interrupt is set by the
Am79C971 controller when a
read or write operation on the MII
management port is complete
from an internal operation. Exam-
ples of internal operations are
Auto-Poll or MII Management
Port generated MII management
frames. These are normally hid-
den to the host.
Complete Internal Interrupt En-
able. If MCCIINTE is set to 1, the
MCCIINT bit will be able to set
the INTR bit when the internal
state machines generate MII
management frames. For in-
stance, when MCCIINTE is set to
1 and the Auto-Poll state ma-
chine generates a MII manage-
ment frame, the MCCIINT will set
the INTR bit upon completion of
the MII management frame re-
gardless of the comparison out-
come.
Management
Management
Management
is
is
set
set
to
Command
Command
Command
to
0
0
by
by