AM79C971AKC\WQOCML AMD (ADVANCED MICRO DEVICES), AM79C971AKC\WQOCML Datasheet - Page 136

• Manufacturer Part Number: AM79C971AKC\WQOCML
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C971AKC\WQOCML

• Operating Supply Voltage (typ): 3.3/5V
• Operating Temperature Classification: Commercial
• Package Type: PQFP
• Mounting: Surface Mount
• Pin Count: 160
• Lead Free Status / Rohs Status: Not Compliant

15-0
CSR36: Next Next Receive Descriptor Address
Lower
Bit
31-16
15-0
CSR37: Next Next Receive Descriptor Address
Upper
Bit
31-16
15-0
CSR38: Next Next Transmit Descriptor Address
Lower
Bit
31-16
15-0
136
CXDAU
Name
RES
NNRDAL
Name
RES
NNRDAU
Name
RES
NNXDAL
current transmit descriptor ad-
dress pointer.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
zeros and read as undefined.
next next receive descriptor ad-
dress pointer.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
zeros and read as undefined.
next next receive descriptor ad-
dress pointer.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
zeros and read as undefined.
next next transmit descriptor ad-
dress pointer.
Read/Write accessible only when
either the STOP or the SPND bit
Contains the upper 16 bits of the
Description
Reserved locations. Written as
Contains the lower 16 bits of the
Description
Reserved locations. Written as
Contains the upper 16 bits of the
Description
Reserved locations. Written as
Contains the lower 16 bits of the
Am79C971
CSR39: Next Next Transmit Descriptor Address
Upper
Bit
31-16 RES
15-0
CSR40: Current Receive Byte Count
Bit
31-16 RES
15-12 RES
11-0
CSR41: Current Receive Status
Bit
31-16 RES
15-0
Name
NNXDAU
Name
CRBC
Name
CRST
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
Description
zeros and read as undefined.
Contains the upper 16 bits of the
next next transmit descriptor ad-
dress pointer.
Description
zeros and read as undefined.
Reserved locations. Read and
written as zeros.
Current Receive Byte Count.
This field is a copy of the BCNT
field of RMD1 of the current re-
ceive descriptor.
Description
zeros and read as undefined.
Current Receive Status. This
field is a copy of bits 31-16 of
RMD1 of the current receive de-
scriptor.
Reserved locations. Written as
Reserved locations. Written as
Reserved locations. Written as