LFXP10C-4F388C Lattice, LFXP10C-4F388C Datasheet - Page 262

• Manufacturer Part Number: LFXP10C-4F388C
• Description: IC FPGA 9.7KLUTS 244I/O 388-BGA
• Manufacturer: Lattice

Specifications of LFXP10C-4F388C

• Lead Free Status / Rohs Status: Contains lead / RoHS non-compliant

Lattice Semiconductor
Dynamic Delay Adjustment
The Dynamic Delay Adjustment is controlled by the DDAMODE input. When the DDAMODE input is set to “1”, the
delay control is handled through the inputs, DDAIZR, DDAILAG and DDAIDEL(2:0). For this mode, the attribute
“DELAY_CNTL” must be set to “DYNAMIC”. Table 11-3 shows the delay adjustment values based on the attri-
bute/input settings.
In this mode, the PLL may come out of lock due to the abrupt change of phase. RST must be asserted to re-lock
the PLL. Upon de-assertion of RST, the PLL will start the lock-in process and will take the t
the PLL lock.
Figure 11-4. Pre-Map Preference Editor
4. EPIC Device Editor: Users can edit their preferences in the EPIC Device Editor as shown in Figure 11-5.
Figure 11-5. EPIC Preferences Edit Window
11-6
sysCLOCK PLL Design and Usage Guide
LatticeECP/EC and LatticeXP
LOCK
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