LFXP10C-4F388C Lattice, LFXP10C-4F388C Datasheet - Page 28
LFXP10C-4F388C
Manufacturer Part Number
LFXP10C-4F388C
Description
IC FPGA 9.7KLUTS 244I/O 388-BGA
Manufacturer
Lattice
Datasheet
1.LFXP3C-3T100C.pdf
(397 pages)
Specifications of LFXP10C-4F388C
Lead Free Status / Rohs Status
Contains lead / RoHS non-compliant
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Lattice Semiconductor
Figure 2-18. Group of Seven PIOs
Figure 2-19. DQS Routing
PIO
The PIO contains four blocks: an input register block, output register block, tristate register block and a control logic
block. These blocks contain registers for both single data rate (SDR) and double data rate (DDR) operation along
with the necessary clock and selection logic. Programmable delay lines used to shift incoming clock and data sig-
nals are also included in these blocks.
Input Register Block
The input register block contains delay elements and registers that can be used to condition signals before they are
passed to the device core. Figure 2-20 shows the diagram of the input register block.
Input signals are fed from the sysIO buffer to the input register block (as signal DI). If desired the input signal can
bypass the register and delay elements and be used directly as a combinatorial signal (INDD), a clock (INCK) and
Four PICs
DQS
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
PIO A
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
2-16
Buffer
sysIO
Delay
Assigned DQS Pin
LatticeXP Family Data Sheet
PADA “T”
PADB “C”
PADA “T”
PADB “C”
PADA “T”
PADB “C”
PADA “T”
PADB “C”
PADA “T”
PADB “C”
PADA “T”
PADB “C”
PADA “T”
PADB “C”
PADB “C”
PADA “T”
PADB “C”
PADA “T”
PADA “T”
PADA “T”
PADB “C”
LVDS Pair
LVDS Pair
LVDS Pair
LVDS Pair
LVDS Pair
LVDS Pair
One PIO Pair
Architecture
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