LFXP20C-5F484C Lattice, LFXP20C-5F484C Datasheet - Page 26
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LFXP20C-5F484C
Manufacturer Part Number
LFXP20C-5F484C
Description
IC FPGA 19.7KLUTS 340I/O 484-BGA
Manufacturer
Lattice
Datasheet
1.LFXP3C-3T100C.pdf
(397 pages)
Specifications of LFXP20C-5F484C
Lead Free Status / Rohs Status
Contains lead / RoHS non-compliant
Available stocks
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Part Number:
LFXP20C-5F484C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
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Figure 2-15. Memory Core Reset
For further information on sysMEM EBR block, see the details of additional technical documentation at the end of
this data sheet.
EBR Asynchronous Reset
EBR asynchronous reset or GSR (if used) can only be applied if all clock enables are low for a clock cycle before the
reset is applied and released a clock cycle after the reset is released, as shown in Figure 2-16. The GSR input to the
EBR is always asynchronous.
Figure 2-16. EBR Asynchronous Reset (Including GSR) Timing Diagram
If all clock enables remain enabled, the EBR asynchronous reset or GSR may only be applied and released after
the EBR read and write clock inputs are in a steady state condition for a minimum of 1/f
release must adhere to the EBR synchronous reset setup time before the next active read or write clock edge.
If an EBR is pre-loaded during configuration, the GSR input must be disabled or the release of the GSR during
device Wake Up must occur before the release of the device I/Os becoming active.
These instructions apply to all EBR RAM and ROM implementations.
Note that there are no reset restrictions if the EBR synchronous reset is used and the EBR GSR input is disabled.
Programmable I/O Cells (PICs)
Each PIC contains two PIOs connected to their respective sysIO Buffers which are then connected to the PADs as
shown in Figure 2-17. The PIO Block supplies the output data (DO) and the Tri-state control signal (TO) to sysIO
buffer, and receives input from the buffer.
GSRN
RSTA
RSTB
Programmable Disable
Reset
Clock
Clock
Enable
Memory Core
2-14
Output Data
L
L
D
D
Latches
CLR
CLR
SET
SET
Q
Q
LatticeXP Family Data Sheet
Port A[17:0]
Port B[17:0]
MAX
(EBR clock). The reset
Architecture
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