LFXP20C-5F484C Lattice, LFXP20C-5F484C Datasheet - Page 311
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LFXP20C-5F484C
Manufacturer Part Number
LFXP20C-5F484C
Description
IC FPGA 19.7KLUTS 340I/O 484-BGA
Manufacturer
Lattice
Datasheet
1.LFXP3C-3T100C.pdf
(397 pages)
Specifications of LFXP20C-5F484C
Lead Free Status / Rohs Status
Contains lead / RoHS non-compliant
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while the other Lattice FPGA devices in the daisy chain operate in Slave Serial mode. The RESET/OE pin of the
PROM is driven by INITN while the Chip Select pin is driven by the DONE pin of the devices.
Figure 13-4. Master and Slave Serial Daisy Chain
Slave Parallel Mode
In Slave Parallel mode a host system sends the configuration data in a byte-wide stream to the device. The CCLK,
CSN, CS1N, and WRITEN pins are driven by the host system. The Slave Parallel configuration mode allows multi-
ple devices to be chained in parallel, as shown in Figure 13-5.
WRITEN, CSN, and CS1N must be held low to write to the device; data is input from D[0:7]. Slave Parallel mode
can also be used for readback of the internal configuration. By driving the WRITEN pin low, and CSN and CS1N
low, the device will input the readback instructions on the D[0:7] pins; WRITEN is then driven high and data read on
D[0:7]. In order to support readback the PERSISTENT bit in ispLEVER’s Preference Editor must be set to ON.
The Slave Parallel mode can support two types of overflow, Bypass and Flow-Through. If the Bypass option is set,
after the first device has received all of its configuration data, the data presented to the D[0:7] pins will be serialized
and bypassed to the DOUT pin. If the Flow-Through option is set, after the first device has received all of its config-
uration data, the CSON signal will drive the following parallel mode device’s chip select low as shown in Figure 13-
5.
To support asynchronous configuration, where the host may provide data faster than the FPGA can accept it, Slave
Parallel mode can use the BUSY signal. By driving the BUSY signal high the Slave Parallel device tells the host to
pause sending data. See Figure 13-6.
Slave Parallel (no overload option)
Slave Parallel (Bypass ON)
Slave Parallel (Flow Through ON)
Configuration Mode
Master Program
RESET/OE
PROM
Serial
DATA
CLK
CS
CCLK
DIN
DONE
INITN
PROGRAMN
CFG[1]
Master Serial
1
1
1
LatticeXP
DOUT
CFG0
CFG1
13-12
CFG[0]
0
0
0
LatticeXP sysCONFIG Usage Guide
CCLK
DIN
DONE
INITN
PROGRAMN
CONFIG_MODE
Slave_Parallel
Slave_Parallel
Slave_Parallel
Slave Serial
LatticeXP
DOUT
CFG1
CFG0
Chain Mode
Flowthrough
Disable
Bypass
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