LFXP20C-5F484C Lattice, LFXP20C-5F484C Datasheet - Page 359
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LFXP20C-5F484C
Manufacturer Part Number
LFXP20C-5F484C
Description
IC FPGA 19.7KLUTS 340I/O 484-BGA
Manufacturer
Lattice
Datasheet
1.LFXP3C-3T100C.pdf
(397 pages)
Specifications of LFXP20C-5F484C
Lead Free Status / Rohs Status
Contains lead / RoHS non-compliant
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Notes on Guided Mapping
All guidance criteria is based on signal name matching. Topology of combinatorial logic is considered when Soft-
wire LUTs (SWLs) exist in the guided file.
Register elements are mapped in two passes. In the first pass, register control signals are matched by name
exactly. In the second pass, the control signals names are not matched. This methodology provides a greater
chance of matching for registers since control signal names have a tendency to change from successive synthesis
runs. Other matching considerations are as follows:
Notes on Guided PAR
To decrease PAR runtimes after minor changes to the physical design file (.ncd), guided PAR uses a previously
placed and/or routed .ncd file to “guide” the placement and routing of the new .ncd file. Guided PAR can be per-
formed from the Project Navigator or specified using the command line -g option with the file name of the guide file.
For PAR to use a guide file for design, PAR first tries to find a guiding object (i.e., nets, components, and/or macros)
in the guide file that corresponds to an object in the new .ncd file. A guiding object is an object in the guide file of
the same name, type, and connectivity as an object in the new .ncd file. A guided object is an object in the new .ncd
file that has a corresponding guiding object in the guide file.
After PAR compares the objects in each file, it places and routes each object of the new .ncd file based on the
placement/routing of its guiding object. If PAR fails to find a guiding object for a component, for example, PAR will
try to find one based on the connectivity. PAR appends the names of all objects which do not have a guiding object
in the guide file to .gpr (Guided PAR Report) file. The matching factor specifies the percentage of the same connec-
tivity that guiding and guided objects must have. It can only be specified using the -mf option in the command line.
The matching factor option applies to nets and components only. When matching factor is 100 (the default), a guid-
ing object must have exactly the same connectivity as the object it is guiding. When a matching factor is specified,
the value specified is taken as the minimum percentage of the same connectivity that a guided object and its guid-
ing object have. Note that the matching factor is always 100 when the guided PAR is performed from the Project
Navigator.
After all guided objects are placed and routed, PAR locks down the locations of all guided components and macros
and then proceeds with its normal operation. Guided PAR supports the following preferences: USE SPINE, USE
PRIMARY, USE SECONDARY, USE LONGLINE, USE HALFLINE, LOCATE COMP, LOCATE MACRO, and hard-
placed PGROUPs.
Conclusion
In general, different designs respond better to different strategies. The processes outlined in this application note
may not be optimal for all cases. For a design's first place and route, run PAR at the low placer effort level and with
a low number of routing iterations. There is no point in running 100 cost tables if the design's logic depth is too high.
The techniques discussed within this document, like interpreting static timing reports and using proper preferences,
will guide the user to better PAR results.
4. Click Close to close the dialog box.
5. Double-click the Place & Route Design process. The ispLEVER software runs the process using the
• For combinatorial logic, new SWLs are matched from SWLs extracted from the guide design.
• All unmatched logic are mapped through the regular mapping process.
• The performance of the guided mapped design can be no better than the original.
• A guide report, <design_name>.gpr, gives details of the success guided map had in matching with the
guide file.
specified guide file.
17-15
Lattice Semiconductor FPGA
Successful Place and Route
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