DJLXT971ALE.A4-835791 Cortina Systems Inc, DJLXT971ALE.A4-835791 Datasheet - Page 45

• Manufacturer Part Number: DJLXT971ALE.A4-835791
• Manufacturer: Cortina Systems Inc

Specifications of DJLXT971ALE.A4-835791

• Lead Free Status / Rohs Status: Not Compliant

LXT971A PHY
Datasheet
249414, Revision 5.2
13 September 2007
5.7.3
Figure 20
5.7.3.1
Cortina Systems
100BASE-X Protocol Sublayer Operations
With respect to the 7-layer communications model, the LXT971A PHY is a Physical Layer
1 (PHY) device.
The LXT971A PHY implements the following sublayers of the reference model defined by
the IEEE 802.3 standard, and discussed from the reference model point of view:
Figure 20
Protocol Sublayers
Physical Coding Sublayer
The Physical Coding Sublayer (PCS) provides the MII interface, as well as the 4B/5B
encoding/decoding function.
For 100BASE-TX and 100BASE-FX operation, the PCS layer provides IDLE symbols to
the PMD-layer line driver as long as TX_EN is de-asserted.
®
•
•
•
•
LXT971A Single-Port 10/100 Mbps PHY Transceiver
Sublayer
Sublayer
Sublayer
Section 5.7.3.1, Physical Coding Sublayer
Section 5.7.3.2, Physical Medium Attachment Sublayer
Section 5.7.3.3, Twisted-Pair Physical Medium Dependent Sublayer
Section 5.7.3.4, Fiber PMD Sublayer
PMA
PMD
PCS
shows the LXT971A PHY protocol sublayers.
LXT97x PHY
De-scrambler
Scrambler /
100BASE-TX
Serializer /De-serializer
Link/Carrier Detect
Encoder /Decoder
MII Interface
Fiber Transceiver
100BASE-FX
LVPECL Interface
5.7 100 Mbps Operation
B3394-02
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