DJLXT971ALE.A4-835791 Cortina Systems Inc, DJLXT971ALE.A4-835791 Datasheet - Page 79

• Manufacturer Part Number: DJLXT971ALE.A4-835791
• Manufacturer: Cortina Systems Inc

Specifications of DJLXT971ALE.A4-835791

• Lead Free Status / Rohs Status: Not Compliant

LXT971A PHY
Datasheet
249414, Revision 5.2
13 September 2007
Table 46
Cortina Systems
Control Register - Address 0, Hex 0
®
1. R/W = Read/Write
2. Some bits have their default values determined at reset by hardware configuration pins. For default details
0.5:0
0.15
0.14
0.13
0.12
0.11
0.10
LXT971A Single-Port 10/100 Mbps PHY Transceiver
Bit
0.9
0.8
0.7
0.6
SC = Self Clearing
for these bits, see
Reset
Loopback
Speed Selection
Auto-Negotiation
Enable
Power-Down
Isolate
Restart Auto-
Negotiation
Duplex Mode
Collision Test
Speed Selection
Reserved
Name
Section 5.4.4, Hardware Configuration Settings
0 = Normal operation
1 = PHY reset
0 = Disable loopback mode
1 = Enable loopback mode
0 = Disable auto-negotiation process
1 = Enable auto-negotiation process
0 = Normal operation
1 = Power-down
0 = Normal operation
1 = Electrically isolate PHY from MII
0 = Normal operation
1 = Restart auto-negotiation process
0 = Half-duplex
1 = Full-duplex
0 = Disable COL signal test
1 = Enable COL signal test
Write as ‘0’. Ignore on Read.
0.6
0.6
0
0
1
1
0
0
1
1
0.13
0.13
0
1
0
1
0
1
0
1
10 Mbps
100 Mbps
1000 Mbps (not supported)
Reserved
10 Mbps
100 Mbps
1000 Mbps (not supported)
Reserved
Description
Speed Selected
Speed Selected
.
8.0 Register Definitions - IEEE
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SC
SC
1
Base Registers
Default
Note 2
Note 2
Note 2
00000
Page 79
0
0
0
0
0
0
0