DJLXT971ALE.A4-835791 Cortina Systems Inc, DJLXT971ALE.A4-835791 Datasheet - Page 93

• Manufacturer Part Number: DJLXT971ALE.A4-835791
• Manufacturer: Cortina Systems Inc

Specifications of DJLXT971ALE.A4-835791

• Lead Free Status / Rohs Status: Not Compliant

LXT971A PHY
Datasheet
249414, Revision 5.2
13 September 2007
Table 61
Table 62
Cortina Systems
Digital Configuration Register - Address 26, Hex 1A (Sheet 2 of 2)
Transmit Control Register - Address 30, Hex 1E
®
26.5:4
26.3
26.2:0
1. R/W = Read /Write, RO = Read Only
30.15:13
30.12
30.11:10
30.4:0
1. Values are approximations and may vary outside indicated values based upon implementation loading
2. R/W = Read/Write
3. Latch State during Reset is based on the state of hardware configuration pins at RESET_L.
LXT971A Single-Port 10/100 Mbps PHY Transceiver
Bit
conditions.
Bit
Reserved
Transmit Low Power
Port Rise Time Control
Reserved
Reserved
Reserved
Reserved
Name
Name
1
Write as ‘0’. Ignore on Read.
Transmit Low Power
0 = Normal transmission.
1 = Forces the transmitter into low power mode.
Port Rise Time Control
00 = 3.0 ns (Default = Setting on TXSLEW[1:0]
01 = 3.4 ns
10 = 3.9 ns
11 = 4.4 ns
Ignore on Read.
Write as ‘0’. Ignore on Read.
Write as ‘0’. Ignore on Read.
Write as ‘0’. Ignore on Read.
Also forces a zero-differential transmission.
pins)
Description
Description
Product-Specific Registers
9.0 Register Definitions -
Type
R/W
R/W
RO
Type
R/W
R/W
R/W
R/W
1
2
Default
Default
Page 93
Note 3
00
000
0
0
0
0