5962-8868907QA QP SEMICONDUCTOR, 5962-8868907QA Datasheet - Page 16

• Manufacturer Part Number: 5962-8868907QA
• Manufacturer: QP SEMICONDUCTOR

Specifications of 5962-8868907QA

• Lead Free Status / Rohs Status: Not Compliant

DSCC FORM 2234
APR 97
1/ All tests must be performed under the worst case conditions.
2/ Guaranteed to the limit specified herein if not tested.
3/ For device types 03, 04, 05, and 06, clock rise and fall times are controlled at approximately 5 ns by the tester.
4/ Tested in interrupt acknowledge cycle only.
5/ Parameter does not apply to interrupt acknowledge transactions.
6/ Float delay is defined as the time required for a 0.5 V change in the output with a maximum dc load and minimum ac load.
7/ Open-drain output, measured with open-drain test load.
8/ Applies to versions with SDLC enhancements only.
9/ Parameter is system dependent. For any SCC in the daisy chain, t
10/ Parameter applies only between transactions involving the SCC.
11/ RxC is RTxC or TRxC, whichever is supplying the receive clock.
12/ Parameter applies only if the data rate is one-fourth the PCLK rate. In all other cases, no phase relationship between RxC
13/ Parameter applies only to FM encoding/decoding.
14/ TxC is TRxC or RTxC, whichever is supplying the transmit clock.
15/ Parameter applies only for transmitter and receiver; DPLL and baud rate generator timing requirements are identical to
16/ The maximum receive or transmit data is one-fourth PCLK.
17/ Both RTxC and SYNC have 30 pF capacitors to ground connected to them.
18/ The value of this parameter is dependent on PCLK cycle time.
TxC
SYNC transition
DCD or CTS
valid delay
2/ 7/ 14/ 18/
to INT valid
delay 2/ 7/ 18/
transition to INT
valid delay
2/ 7/ 18/
highest priority device in the daisy chain, t
chain.
and PCLK or TxC and PCLK is required.
chip PCLK requirements.
to INT
Test
DEFENSE SUPPLY CENTER COLUMBUS
MICROCIRCUIT DRAWING
COLUMBUS, OHIO 43216-5000
t
t
t
STANDARD
dTXC(INT)
dSY(INT)
dEXT(INT)
Symbol
TABLE I. Electrical performance characteristics – Continued.
See figure 3, system
timings.
C
V
unless otherwise specified
L
CC
= 50 pF 10%
-55 C
= 4.5 V
V
CC
Conditions 1/
sIEI(RDA)
= 5.0 V 10%
T
C
for the SCC, and t
+125 C
subgroups
9, 10, 11
9, 10, 11
9, 10, 11
Group A
dIAi(RD)
dIEIf(IEO)
SIZE
A
must be greater than the sum of t
for each device seperating them in the daisy
Ref
10
no.
REVISION LEVEL
8
9
01,02,03,
04,05,06,
01,02,03,
04,05,06,
08,09,10
07,08,09
Device
type
07
All
10
C
Min
9
6
2
3
2
Limits
dPC(IEO)
SHEET
5962-88689
Max
13
10
6
8
6
for the
16
t
t
t
Unit
cPC
cPC
cPC