5962-8868907QA QP SEMICONDUCTOR, 5962-8868907QA Datasheet - Page 27

• Manufacturer Part Number: 5962-8868907QA
• Manufacturer: QP SEMICONDUCTOR

Specifications of 5962-8868907QA

• Lead Free Status / Rohs Status: Not Compliant

DSCC FORM 2234
APR 97
6.6 Pin descriptions – Continued.
RTxCA, RTxCB
DEFENSE SUPPLY CENTER COLUMBUS
D/C
DCDA, DCDB
D
DTR/REQA,
DTR/REQB
IEI
IEO
INT
INTACK
PCLK
RD
RxDA, RxDB
0
-D
MICROCIRCUIT DRAWING
7
COLUMBUS, OHIO 43216-5000
STANDARD
Receive/transmit clocks (inputs, active low). These pins can be programmed in several
different modes of operation. In each channel, RTxC may supply the receive clock, the
transmit clock, the clock for the baud rate generator, or the clock for the digital phase-locked
loop. These pins can also be programmed for use with the respective SYNC pins as a crystal
oscillator. The receive clock may be 1, 16, 32, or 64 times the data rate in asynchronous
modes.
Data/control select (input). This signal defines the type of information transferred to or from
the SCC. A high means data is transferred, a low indicates a command.
programmed for auto enables; otherwise they may be used as general-purpose input pins.
Both pins are Schmitt-trigger buffered to accommodate slow rise time signals. The SCC
detects pulses on these pins and can interrupt the CPU on both logic level transitions.
Data bus (bidirectional, three-state). These lines carry data and commands to and from the
SCC.
Data terminal ready/request (outputs, active low). These outputs follow the state
programmed into the DTR bit. They can also be used as general purpose outputs or as
request lines for a DMA controller.
Interrupt enable in (input, active high). IEI is used with IEO to form an interrupt daisy chain
when there is more than one interrupt driven device. A high IEI indicates that no other higher
priority device has an interrupt under service or is requesting an interrupt.
Interrupt enable out (output, active high). IEO is high only if IEI is high and the CPU is not
servicing an SCC interrupt or the SCC is not requesting an interrupt (interrupt acknowledge
cycle only). IEO is connected to the next lower priority device's IEI input and thus inhibits
interrupts from lower priority devices.
Interrupt request (output, open-drain, active low). This signal is activated when the SCC
requests an interrupt.
Interrupt acknowledge (input, active low). This signal indicates an active interrupt
acknowledge cycle. During this cycle, the SCC interrupt daisy chain settles. When RD
becomes active, the SCC places an interrupt vector on the data bus (if IEI is high). INTACK is
latched by the rising edge of PCLK.
Clock (input). This is the master SCC clock used to synchronize internal signals. PCLK is a
TTL level signal. PCLK is not required to have any phase relationship with the master system
clock.
Read (input, active low). This signal indicates a read operation and when the SCC is selected,
enables the SCC's bus drivers. During the interrupt acknowledge cycle, this signal gates the
interrupt vector onto the bus if the SCC is the highest priority device requesting an interrupt.
Receive data (inputs, active high). These input signals receive serial data at standard TTL
levels.
Data carrier detect (inputs, active low). These pins function as receiver enables if they are
SIZE
A
REVISION LEVEL
C
SHEET
5962-88689
27