AT24C512C-XHM-B Atmel, AT24C512C-XHM-B Datasheet - Page 8

• Manufacturer Part Number: AT24C512C-XHM-B
• Manufacturer: Atmel

Specifications of AT24C512C-XHM-B

• Lead Free Status / Rohs Status: Compliant

5.
6.
8
Figure 4-6.
Device Addressing
The 512K EEPROM requires an 8-bit device address word following a start condition to enable the chip for a read or write
operation (see
four most-significant bits, as shown. This is common to all two-wire EEPROM devices.
The 512K uses the three device address bits A2, A1, and A0 to allow as many as eight devices on the same bus. These
bits must compare to their corresponding hardwired input pins. The A2, A1, and A0 pins use an internal proprietary circuit
that biases them to a logic low condition if the pins are allowed to float.
The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high and
a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a zero. If a compare is not made, the device will return to
a standby state.
DATA SECURITY: The Atmel
the whole memory when the WP pin is at V
Write Operations
BYTE WRITE: A write operation requires two 8-bit data word addresses following the device address word and
acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the first 8-bit
data word. Following receipt of the 8-bit data word, the EEPROM will output a zero. The addressing device, such as a
microcontroller, then must terminate the write sequence with a stop condition. At this time, the EEPROM enters an
internally-timed write cycle, t
EEPROM will not respond until the write is complete (see
PAGE WRITE: The 512K EEPROM is capable of 128-byte page writes.
A page write is initiated the same way as a byte write, but the microcontroller does not send a stop condition after the first
data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can
transmit up to 127 more data words. The EEPROM will respond with a zero after each data word received. The
microcontroller must terminate the page write sequence with a stop condition (see
DATA OUT
Atmel AT24C512C
DATA IN
SCL
Output Acknowledge
Figure 7-1 on page
START
1
®
WR
AT24C512C has a hardware data protection scheme that allows the user to write protect
, to the nonvolatile memory. All inputs are disabled during this write cycle, and the
9). The device address word consists of a mandatory one-zero sequence for the first
CC
.
8
Figure 7-2 on page
ACKNOWLEDGE
9
10).
Figure 7-3 on page
10).
8720A–SEEPR–9/10