AT24C512C-XHM-B Atmel, AT24C512C-XHM-B Datasheet - Page 9

• Manufacturer Part Number: AT24C512C-XHM-B
• Manufacturer: Atmel

Specifications of AT24C512C-XHM-B

• Lead Free Status / Rohs Status: Compliant

Atmel AT24C512C
The data word address lower seven bits are internally incremented following the receipt of each data word. The higher
data word address bits are not incremented, retaining the memory page row location. When the word address, internally
generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than 128
data words are transmitted to the EEPROM, the data word address will “roll over” and previous data will be overwritten.
The address roll over during write is from the last byte of the current page to the first byte of the same page.
ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the EEPROM inputs are disabled,
acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The
Read/Write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM
respond with a zero, allowing the read or write sequence to continue.
7.
Read Operations
Read operations are initiated the same way as write operations with the exception that the Read/Write select bit in the
device address word is set to one. There are three read operations: current address read, random address read, and
sequential read.
CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during the last
read or write operation, incremented by one. This address stays valid between operations as long as the chip power is
maintained. The address roll over during read is from the last byte of the last memory page to the first byte of the first
page.
Once the device address with the Read/Write select bit set to one is clocked in and acknowledged by the EEPROM, the
current address data word is serially clocked out. The microcontroller does not respond with an input zero, but does
generate a following stop condition (see
Figure 7-4 on page
10).
RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data word address. Once the
device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must
generate another start condition. The microcontroller now initiates a current address read by sending a device address with
the Read/Write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The
microcontroller does not respond with a zero, but does generate a following stop condition (see
Figure 7-5 on page
10).
SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read. After the
microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge,
it will continue to increment the data word address and serially clock out sequential data words. When the memory
address limit is reached, the data word address will roll over and the sequential read will continue. The sequential read
operation is terminated when the microcontroller does not respond with a zero but does generate a following stop
condition (see
Figure 7-6 on page
10).
Figure 7-1.
Device Address
1
0
1
0
A2
A1
A0
R/W
LSB
MSB
9
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