PCF8563P NXP Semiconductors, PCF8563P Datasheet - Page 21

PCF8563P

Manufacturer Part Number
PCF8563P
Description
Manufacturer
NXP Semiconductors
Datasheet

Specifications of PCF8563P

Bus Type
Serial (2-Wire, I2C)
Date Format
DW:DM:M:Y
Time Format
HH:MM:SS
Operating Supply Voltage (typ)
2.5/3.3/5V
Package Type
PDIP
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
1.8V
Operating Temperature Classification
Industrial
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Pin Count
8
Mounting
Through Hole
Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PCF8563P
Manufacturer:
NXP
Quantity:
5 510
Part Number:
PCF8563P
Manufacturer:
NXP
Quantity:
10 000
Part Number:
PCF8563P
Manufacturer:
PHILIPS/飞利浦
Quantity:
20 000
Part Number:
PCF8563P/F4
Manufacturer:
PULES
Quantity:
2 450
Part Number:
PCF8563P/F4
Manufacturer:
NXP/恩智浦
Quantity:
20 000
Part Number:
PCF8563P/F4112
Manufacturer:
NXP Semiconductors
Quantity:
1 912
NXP Semiconductors
9. Characteristics of the I
PCF8563
Product data sheet
9.1 Bit transfer
9.2 START and STOP conditions
9.3 System configuration
The I
The two lines are a Serial DAta line (SDA) and a Serial Clock Line (SCL). Both lines must
be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only
when the bus is not busy.
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as a control signal (see
Both data and clock lines remain HIGH when the bus is not busy.
A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START
condition - S.
A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition - P (see
A device generating a message is a transmitter; a device receiving a message is a
receiver. The device that controls the message is the master; and the devices which are
controlled by the master are the slaves (see
Fig 14. Bit transfer
Fig 15. Definition of START and STOP conditions
2
C-bus is for bidirectional, two-line communication between different ICs or modules.
SDA
SCL
START condition
All information provided in this document is subject to legal disclaimers.
2
SDA
SCL
Figure
C-bus
S
Rev. 7 — 23 July 2010
15).
data valid
data line
stable;
Figure
Figure
allowed
change
of data
14).
16).
STOP condition
Real-time clock/calendar
mbc621
P
PCF8563
© NXP B.V. 2010. All rights reserved.
mbc622
SDA
SCL
21 of 44

Related parts for PCF8563P