P89C51RB2HBA NXP Semiconductors, P89C51RB2HBA Datasheet - Page 26

• Manufacturer Part Number: P89C51RB2HBA
• Manufacturer: NXP Semiconductors

Specifications of P89C51RB2HBA

• Cpu Family: 89C
• Device Core: 80C51
• Device Core Size: 8b
• Frequency (max): 33MHz
• Interface Type: UART
• Program Memory Type: Flash
• Program Memory Size: 16KB
• Total Internal Ram Size: 512Byte
• # I/os (max): 32
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PLCC
• Lead Free Status / Rohs Status: Not Compliant

Philips Semiconductors
2002 May 24
80C51 8-bit Flash microcontroller family
16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM
NOTE:
* User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive
** f
NOTE:
* User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive
Symbol
CIDL
WDTE
–
CPS1
CPS0
ECF
Symbol
CF
CR
–
CCF4
CCF3
CCF2
CCF1
CCF0
value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.
value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.
OSC
= oscillator frequency
Bit:
Bit Addressable
Bit:
Function
Counter Idle control: CIDL = 0 programs the PCA Counter to continue functioning during idle Mode. CIDL = 1 programs
it to be gated off during idle.
Watchdog Timer Enable: WDTE = 0 disables Watchdog Timer function on PCA Module 4. WDTE = 1 enables it.
Not implemented, reserved for future use.*
PCA Count Pulse Select bit 1.
PCA Count Pulse Select bit 0.
CPS1
PCA Enable Counter Overflow interrupt: ECF = 1 enables CF bit in CCON to generate an interrupt. ECF = 0 disables
that function of CF.
Function
PCA Counter Overflow flag. Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF in CMOD is
set. CF may be set by either hardware or software but can only be cleared by software.
PCA Counter Run control bit. Set by software to turn the PCA counter on. Must be cleared by software to turn the PCA
counter off.
Not implemented, reserved for future use*.
PCA Module 4 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
PCA Module 3 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
PCA Module 2 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
PCA Module 1 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
PCA Module 0 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
CMOD Address = D9H
0
0
1
1
CCON Address = D8H
CIDL
7
CF
7
CPS0
0
1
0
1
WDTE
Selected PCA Input**
CR
6
6
0
1
2
3
Figure 18. CCON: PCA Counter Control Register
Figure 17. CMOD: PCA Counter Mode Register
–
5
Internal clock, f
Internal clock, f
Timer 0 overflow
External clock at ECI/P1.2 pin
5
–
(max. rate = f
CCF4
–
4
4
OSC
OSC
OSC
/6 in 6-clock mode (f
/2 in 6-clock mode (f
/4 in 6-clock mode, f
23
CCF3
–
3
3
CPS1
CCF2
2
2
OSC
OSC
OCS
CCF1
/12 in 12-clock mode)
/4 in 12-clock mode)
CPS0
/8 in 12-clock mode)
P89C51RB2/P89C51RC2/
1
1
CCF0
ECF
0
0
Reset Value = 00XX X000B
Reset Value = 00X0 0000B
P89C51RD2Hxx
SU01318
SU01319
Product data