P89C51RB2HBA NXP Semiconductors, P89C51RB2HBA Datasheet - Page 44

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P89C51RB2HBA

Manufacturer Part Number
P89C51RB2HBA
Description
Manufacturer
NXP Semiconductors
Datasheet

Specifications of P89C51RB2HBA

Cpu Family
89C
Device Core
80C51
Device Core Size
8b
Frequency (max)
33MHz
Interface Type
UART
Program Memory Type
Flash
Program Memory Size
16KB
Total Internal Ram Size
512Byte
# I/os (max)
32
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4.5V
Instruction Set Architecture
CISC
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
44
Package Type
PLCC
Lead Free Status / Rohs Status
Not Compliant

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Philips Semiconductors
Power-On Reset Code Execution
The P89C51RB2/RC2/RD2Hxx contains two special Flash registers:
the BOOT VECTOR and the STATUS BYTE. At the falling edge of
reset, the P89C51RB2/RC2/RD2Hxx examines the contents of the
Status Byte. If the Status Byte is set to zero, power-up execution
starts at location 0000H, which is the normal start address of the
user’s application code. When the Status Byte is set to a value other
than zero, the contents of the Boot Vector is used as the high byte of
the execution address and the low byte is set to 00H. The factory
default setting is 0FCH, corresponds to the address 0FC00H for the
factory masked-ROM ISP boot loader. A custom boot loader can be
written with the Boot Vector set to the custom boot loader.
NOTE: When erasing the Status Byte or Boot Vector, both
bytes are erased at the same time. It is necessary to reprogram
the Boot Vector after erasing and updating the Status Byte.
Hardware Activation of the Boot Loader
The boot loader can also be executed by holding PSEN LOW, P2.7,
P2.6 high, EA greater than V
2002 May 24
80C51 8-bit Flash microcontroller family
16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM
89C51RD2Hxx
IH
89C51RC2Hxx
(such as +5 V), and ALE HIGH (or not
89C51RB2Hxx
PROGRAM
ADDRESS
Figure 43. Flash Memory Configurations
FFFF
C000
8000
4000
2000
0000
41
BLOCK 4
BLOCK 3
BLOCK 2
BLOCK 1
BLOCK 0
If the factory default setting for the Boot Vector (0FCH) is changed, it
After programming the Flash, the status byte should be programmed
16 kB
16 kB
16 kB
connected) at the falling edge of RESET. This is the same effect as
having a non-zero status byte. This allows an application to be built
that will normally execute the end user’s code but can be manually
forced into ISP operation.
will no longer point to the ISP masked-ROM boot loader code. If this
happens, the only way it is possible to change the contents of the
Boot Vector is through the parallel programming method, provided
that the end user application does not contain a customized loader
that provides for erasing and reprogramming of the Boot Vector and
Status Byte.
to zero in order to allow execution of the user’s application code
beginning at address 0000H.
8 kB
8 kB
P89C51RB2/P89C51RC2/
BOOT ROM
(1 kB)
P89C51RD2Hxx
FFFF
FC00
SU01298
Product data

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