P89C51RB2HBA NXP Semiconductors, P89C51RB2HBA Datasheet - Page 32

• Manufacturer Part Number: P89C51RB2HBA
• Manufacturer: NXP Semiconductors

Specifications of P89C51RB2HBA

• Cpu Family: 89C
• Device Core: 80C51
• Device Core Size: 8b
• Frequency (max): 33MHz
• Interface Type: UART
• Program Memory Type: Flash
• Program Memory Size: 16KB
• Total Internal Ram Size: 512Byte
• # I/os (max): 32
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PLCC
• Lead Free Status / Rohs Status: Not Compliant

Philips Semiconductors
Expanded Data RAM Addressing
The P89C51RB2/RC2/RD2Hxx has internal data memory that is
mapped into four separate segments: the lower 128 bytes of RAM,
upper 128 bytes of RAM, 128 bytes Special Function Register (SFR),
and 256 bytes expanded RAM (ERAM) (768 bytes for the RD2).
The four segments are:
1. The Lower 128 bytes of RAM (addresses 00H to 7FH) are
2. The Upper 128 bytes of RAM (addresses 80H to FFH) are
3. The Special Function Registers, SFRs, (addresses 80H to FFH)
4. The 256/768-bytes expanded RAM (ERAM, 00H – 1FFH/2FFH)
The Lower 128 bytes can be accessed by either direct or indirect
addressing. The Upper 128 bytes can be accessed by indirect
addressing only. The Upper 128 bytes occupy the same address
space as the SFR. That means they have the same address, but are
physically separate from SFR space.
When an instruction accesses an internal location above address
7FH, the CPU knows whether the access is to the upper 128 bytes
of data RAM or to SFR space by the addressing mode used in the
instruction. Instructions that use direct addressing access SFR
space. For example:
accesses the SFR at location 0A0H (which is P2). Instructions that
use indirect addressing access the Upper 128 bytes of data RAM.
2002 May 24
80C51 8-bit Flash microcontroller family
16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM
MOV 0A0H,#data
directly and indirectly addressable.
indirectly addressable only.
are directly addressable only.
are indirectly accessed by move external instruction, MOVX, and
with the EXTRAM bit cleared, see Figure 27.
NOTE:
*User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new
bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.
AUXR
Symbol
AO
EXTRAM
—
0
Address = 8EH
Not Bit Addressable
Bit:
Function
Disable/Enable ALE
AO
1
Internal/External RAM access using MOVX @Ri/@DPTR
EXTRAM
0
1
Not implemented, reserved for future use*.
—
7
Operating Mode
ALE is emitted at a constant rate of
ALE is active only during a MOVX or MOVC instruction.
Operating Mode
Internal ERAM access using MOVX @Ri/@DPTR
External data memory access.
—
6
—
5
Figure 27. AUXR: Auxiliary Register
—
4
29
1
/
3
—
3
the oscillator frequency (6 clock mode;
For example:
where R0 contains 0A0H, accesses the data byte at address 0A0H,
rather than P2 (whose address is 0A0H).
The ERAM can be accessed by indirect addressing, with EXTRAM
bit cleared and MOVX instructions. This part of memory is physically
located on-chip, logically occupies the first 256/768-bytes of external
data memory in the P89C51RB2/RC2/P89C51RD2
With EXTRAM = 0, the ERAM is indirectly addressed, using the
MOVX instruction in combination with any of the registers R0, R1 of
the selected bank or DPTR. An access to ERAM will not affect ports
P0, P3.6 (WR#) and P3.7 (RD#). P2 SFR is output during external
addressing. For example, with EXTRAM = 0,
where R0 contains 0A0H, access the ERAM at address 0A0H rather
than external memory. An access to external data memory locations
higher than the ERAM will be performed with the MOVX DPTR
instructions in the same way as in the standard 80C51, so with P0
and P2 as data/address bus, and P3.6 and P3.7 as write and read
timing signals. Refer to Figure 28.
With EXTRAM = 1, MOVX @Ri and MOVX @DPTR will be similar
to the standard 80C51. MOVX @ Ri will provide an 8-bit address
multiplexed with data on Port 0 and any output port pins can be
used to output higher order address bits. This is to provide the
external paging capability. MOVX @DPTR will generate a 16-bit
address. Port 2 outputs the high-order eight address bits (the
contents of DPH) while Port 0 multiplexes the low-order eight
address bits (DPL) with data. MOVX @Ri and MOVX @DPTR will
generate either read or write signals on P3.6 (WR) and P3.7 (RD).
The stack pointer (SP) may be located anywhere in the 256 bytes
RAM (lower and upper RAM) internal data memory. The stack may
not be located in the ERAM.
MOV @R0,acc
MOVX @R0,acc
—
2
EXTRAM
P89C51RB2/P89C51RC2/
1
AO
0
Reset Value = xxxx xx00B
P89C51RD2Hxx
1
/
6
f
OSC
in 12 clock mode).
Product data
SU01258