LH28F008BJT-BTLZ1 Sharp Electronics, LH28F008BJT-BTLZ1 Datasheet - Page 11

• Manufacturer Part Number: LH28F008BJT-BTLZ1
• Manufacturer: Sharp Electronics

Specifications of LH28F008BJT-BTLZ1

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 100ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 20b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 1M
• Supply Current: 30mA
• Mounting: Surface Mount
• Pin Count: 40
• Lead Free Status / Rohs Status: Not Compliant

2.1 Data Protection
When V
altered. The CUI, with two-step block erase, full chip
erase, byte write or lock-bit configuration command
sequences, provides protection from unwanted operations
even when high voltage is applied to V
functions are disabled when V
lockout voltage V
block locking capability provides additional protection
from inadvertent code or data alteration by gating block
erase, full chip erase and byte write operations. Refer to
Table 5 for write protection alternatives.
3 BUS OPERATION
The local CPU reads and writes flash memory in-system.
All bus cycles to or from the flash memory conform to
standard microprocessor bus cycles.
3.1 Read
Information can be read from any block, identifier codes
or status register independent of the V
can be at V
The first task is to write the appropriate read mode
command (Read Array, Read Identifier Codes or Read
Status Register) to the CUI. Upon initial device power-up
or after exit from reset mode, the device automatically
resets to read array mode. Five control pins dictate the
data flow in and out of the component: CE#, OE#, WE#,
RP# and WP#. CE# and OE# must be driven active to
obtain data at the outputs. CE# is the device selection
control, and when active enables the selected memory
device. OE# is the data output (DQ
when active drives the selected memory data onto the I/O
bus. WE# must be at V
must be at V
3.2 Output Disable
With OE# at a logic-high level (V
are disabled. Output pins (DQ
impedance state.
3.3 Standby
CE# at a logic-high level (V
standby mode which substantially reduces device power
consumption. DQ
impedance state independent of OE#. If deselected during
block erase, full chip erase, byte write or lock-bit
configuration, the device continues functioning, and
consuming active power until the operation completes.
sharp
CCW
IH
IL
.
≤V
or V
CCWLK
LKO
0
IH
-DQ
. Figure 14 illustrates read cycle.
or when RP# is at V
7
IH
, memory contents cannot be
, RP# must be at V
outputs are placed in a high-
0
-DQ
IH
CC
) places the device in
IH
7
) are placed in a high-
), the device outputs
is below the write
0
-DQ
CCW
IL
CCW
7
. The device’s
) control and
voltage. RP#
IH
. All write
, and WP#
LHF08JZ1
3.4 Reset
RP# at V
In read modes, RP#-low deselects the memory, places
output drivers in a high-impedance state and turns off all
internal circuits. RP# must be held low for a minimum of
100ns. Time t
mode until initial memory access outputs are valid. After
this wake-up interval, normal operation is restored. The
CUI is reset to read array mode and status register is set to
80H.
During block erase, full chip erase, byte write or lock-bit
configuration modes, RP#-low will abort the operation.
SR.7 remains "0" until the reset operation is complete.
Memory contents being altered are no longer valid; the
data may be partially erased or written. Time t
required after RP# goes to logic-high (V
command can be written.
As with any automated device, it is important to assert
RP# during system reset. When the system comes out of
reset, it expects to read from the flash memory. Automated
flash memories provide status information when accessed
during block erase, full chip erase, byte write or lock-bit
configuration modes. If a CPU reset occurs with no flash
memory reset, proper CPU initialization may not occur
because the flash memory may be providing status
information instead of array data. SHARP’s flash
memories allow proper CPU initialization following a
system reset through the use of the RP# input. In this
application, RP# is controlled by the same RESET# signal
that resets the system CPU.
3.5 Read Identifier Codes
The
manufacturer code, device code, block lock configuration
codes for each block and the permanent lock configuration
code (see Figure 4). Using the manufacturer and device
codes, the system CPU can automatically match the device
with its proper algorithms. The block lock and permanent
lock configuration codes identify locked and unlocked
blocks and permanent lock-bit setting.
read
IL
initiates the reset mode.
identifier
PHQV
is required after return from reset
codes
operation
IH
) before another
outputs
Rev. 1.27
PHWL
the
8
is