LH28F008BJT-BTLZ1 Sharp Electronics, LH28F008BJT-BTLZ1 Datasheet - Page 6

• Manufacturer Part Number: LH28F008BJT-BTLZ1
• Manufacturer: Sharp Electronics

Specifications of LH28F008BJT-BTLZ1

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 100ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 20b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 1M
• Supply Current: 30mA
• Mounting: Surface Mount
• Pin Count: 40
• Lead Free Status / Rohs Status: Not Compliant

1 INTRODUCTION
This datasheet contains the product specifications. Section
1 provides a flash memory overview. Sections 2, 3, 4 and
5 describe the memory organization and functionality.
Section 6 covers electrical specifications.
1.1 Features
Key enhancements of the product are:
Please note following:
1.2 Product Overview
The product is a high-performance 8M-bit Boot Block
Flash memory organized as 1M-byte of 8 bits. The 1M-
byte of data is arranged in two 8K-byte boot blocks, six
8K-byte parameter blocks and fifteen 64K-byte main
blocks which are individually erasable, lockable and
unlockable in-system. The memory map is shown in
Figure 3.
The dedicated V
when V
sharp
•Single low voltage operation
•Low power consumption
•Enhanced Suspend Capabilities
•Boot Block Architecture
•V
3.6V block erase, full chip erase, byte write and lock-
bit configuration operations. The V
transitions to GND is recommended for designs that
switch V
CCWLK
CCW
CCW
≤V
has been lowered to 1.0V to support 2.7V-
CCWLK
CCW
off during read operation.
.
pin gives complete data protection
CCW
voltage
LHF08JZ1
A Command User Interface (CUI) serves as the interface
between the system processor and internal operation of the
device. A valid command sequence written to the CUI
initiates device automation. An internal Write State
Machine (WSM) automatically executes the algorithms
and timings necessary for block erase, full chip erase, byte
write and lock-bit configuration operations.
A block erase operation erases one of the device’s 64K-
byte blocks typically within 1.2s (3V V
8K-byte blocks typically within 0.6s (3V V
independent of other blocks. Each block can be
independently erased minimum 100,000 times. Block
erase suspend mode allows system software to suspend
block erase to read or write data from any other block.
Writing memory data is performed in byte increments of
the device’s 64K-byte blocks typically within 33µs (3V
V
(3V V
the system to read data or execute code from any other
flash memory array location.
Individual block locking uses a combination of bits,
twenty-three block lock-bits, a permanent lock-bit and
WP# pin, to lock and unlock blocks. Block lock-bits gate
block erase, full chip erase and byte write operations,
while the permanent lock-bit gates block lock-bit
modification and locked block alternation. Lock-bit
configuration operations (Set Block Lock-Bit, Set
Permanent
commands) set and cleared lock-bits.
The status register indicates when the WSM’s block erase,
full chip erase, byte write or lock-bit configuration
operation is finished.
CC
, 3V V
CC
, 3V V
CCW
Lock-Bit
), 8K-byte blocks typically within 36µs
CCW
). Byte write suspend mode enables
and
Clear
Block
CC
CC
, 3V V
, 3V V
Lock-Bits
Rev. 1.27
CCW
CCW
3
),
)