LH28F160BVHE-BTL90 Sharp Electronics, LH28F160BVHE-BTL90 Datasheet - Page 14

• Manufacturer Part Number: LH28F160BVHE-BTL90
• Manufacturer: Sharp Electronics

Specifications of LH28F160BVHE-BTL90

• Cell Type: NOR
• Density: 16Mb
• Access Time (max): 90ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 21/20Bit
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 2M/1M
• Supply Current: 30mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Not Compliant

The status register may be read to determine when a block
erase or word/byte
writing
command is written.
latched on the falling edge of OE# or CE#, whichever
occurs. OE# or CE# must toggle to V,, before further
reads to update the status register latch. The Read Status
Register command functions independently of the V,,
voltage. RP# can be V,, or V,,.
4.3 Read Status Register Command
operation completed successfully. It may be read at any
time by writing the Read Status Register command. After
output data from the status register until another valid
This operation is also initiated by-writing
The Read Array command functions independently of the
V,, voltage and RP# can be V,, or V,.
4.2 Read Identifier Codes Command
The identifier code operation is initiated by writing the
Read Identifier Codes command. Following the command
write, read cycles from addresses shown in Figure 4
retrieve the manufacturer and device codes (see Table 5
for identifier code values). To terminate the operation,
write
command, the Read Identifier Codes command functions
independently of the V,
V,.
following information can be read:
4.1 Read Array Command
Upon initial device power-up and after exit from deep
power-down mode, the device defaults to read array mode.
command. The device remains enabled for reads until
another command is written. Once the internal WSM has
started a block erase or word/byte write, the device will
not recognize the Read Array command until the WSM
completes its operation unless the WSM is suspended via
an Erase Suspend or Word/Byte Write Suspend command.
SHARP
Following the Read Identifier Codes command, the
another valid command. Like the Read Array
this command, all subsequent read operations
Table 5. Identifier Codes
write is complete and whether the
The status register contents are
voltage and RP# can be V,
the Read Array
LHF16Vll
or
This two-step command sequence of set-up followed by
execution ensures that block contents are not accidentally
erased. An invalid Block Erase command sequence will
result in both status register bits SR.4 and SR.5 being set
to “1”. Also, reliable block erasure can only occur when
V,,=2.7V-3.6V
high voltage, block contents are protected against erasure.
If block erase is attempted while V,&V,,,,,
SR.5 will be set to “1”. Successful block erase for boot
blocks
WP#=V,,
boot block
RP#=V,,,
operations with V,,<RP#<VBB
and should not be attempted.
Erase is executed one block at a time and initiated by a
within the block to be erased (erase changes all block data
to FFFFH). Block preconditioning, erase, and verify are
handled internally by the WSM (invisible to the system).
After the two-cycle
device automatically outputs status register data when read
by analyzing the output data of the RY/BY# pin or status
register bit SR.7.
When the block erase is complete, status register bit SR.5
should be checked. If a block erase error is detected, the
status register should be cleared before system software
attempts corrective actions. The CUI remains in read
status register mode until a new command is issued.
4.4 Clear Status Register Command
Register command. These bits indicate various failure
conditions (see Table 7). By allowing system software to
reset these bits, several operations (such as cumulatively
erasing multiple blocks or writing several words/bytes in
polled to determine if an error occurred during the
sequence.
To clear the status register, the Clear Status Register
command (50H) is written. It functions independently of
the applied V,, Voltage. RP# can be V,, or V,.
command is not functional
word/byte write suspend modes.
4.5 Block Erase Command
two-cycle command. A block erase setup is first written,
followed
sequence requires appropriate sequencing and an address
(see Figure 5). The CPU can detect block erase completion
Status register bits SR.5, SR.4, SR.3 or SR.l are set to
“1”s by the WSM and can only be reset by the Clear Status
sequence) may be performed. The status register may be
requires
by an block erase confirm.
SR.l and SR.5 will be set to “1”. Block erase
or’RP#=VBB.
when
and VPP=Vr,PH1,2. In the absence of this
that the corresponding
block erase sequence is written, the
the corresponding
If block erase is attempted to
during
produce spurious results
block
This command
WP#=V,,
if set, that
Rev. 1.02
SR.3 and
erase or
This
12
or