LH28F320S5HNS-ZP Sharp Electronics, LH28F320S5HNS-ZP Datasheet - Page 8

• Manufacturer Part Number: LH28F320S5HNS-ZP
• Manufacturer: Sharp Electronics

Specifications of LH28F320S5HNS-ZP

• Cell Type: NOR
• Density: 32Mb
• Access Time (max): 100ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 22/21Bit
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: -40C to 85C
• Package Type: SSOP
• Program/erase Volt (typ): 4.5 to 5.5V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8/16Bit
• Number Of Words: 4M/2M
• Supply Current: 75mA
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / Rohs Status: Compliant

DQ
Symbol
BYTE#
A
CE
CE
WE#
WP#
GND
RP#
OE#
STS
V
V
0
0
NC
-A
-DQ
CC
PP
0
1
#,
21
#
15
OUTPUT
OUTPUT
SUPPLY
SUPPLY
SUPPLY GROUND: Do not float any ground pins.
INPUT/
DRAIN
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
OPEN
Type
ADDRESS INPUTS: Inputs for addresses during read and write operations. Addresses are
internally latched during a write cycle.
A
A
A
A
DATA INPUT/OUTPUTS:
DQ
array, status register, query, and identifier code read cycles. Data pins float to high-
impedance when the chip is deselected or outputs are disabled. Data is internally latched
during a write cycle.
DQ
array read cycles in x16 mode; not used for status register, query and identifier code read
mode. Data pins float to high-impedance when the chip is deselected, outputs are
disabled, or in x8 mode(Byte#=V
CHIP ENABLE: Activates the device’s control logic, input buffers decoders, and sense
amplifiers. Either CE
to standby levels. Both CE
RESET/DEEP POWER-DOWN: Puts the device in deep power-down mode and resets
internal automation. RP# V
write operations which provides data protection during power transitions. Exit from deep
power-down sets the device to read array mode.
OUTPUT ENABLE: Gates the device’s outputs during a read cycle.
WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are
latched on the rising edge of the WE# pulse.
STS (RY/BY#): Indicates the status of the internal WSM. When configured in level mode
(default mode), it acts as a RY/BY# pin. When low, the WSM is performing an internal
operation (block erase, full chip erase, (multi) word/byte write or block lock-bit
configuration). STS High Z indicates that the WSM is ready for new commands, block
erase is suspended, and (multi) word/byte write is inactive, (multi) word/byte write is
suspended or the device is in deep power-down mode. For alternate configurations of the
STATUS pin, see the Configuration command.
WRITE PROTECT: Master control for block locking. When V
erased and programmed, and block lock-bits can not be set and reset.
BYTE ENABLE: BYTE# V
DQ
input buffer.
BLOCK ERASE, FULL CHIP ERASE, (MULTI) WORD/BYTE WRITE, BLOCK LOCK-
BIT CONFIGURATION POWER SUPPLY: For erasing array blocks, writing bytes or
configuring block lock-bits. With V
erase, full chip erase, (multi) word/byte write and block lock-bit configuration with an invalid
V
DEVICE POWER SUPPLY: Internal detection configures the device for 5V operation. Do
not float any power pins. With V
inhibited. Device operations at invalid V
spurious results and should not be attempted.
NO CONNECT: Lead is not internal connected; it may be driven or floated.
0
1
5
16
PP
: Byte Select Address. Not used in x16 mode(can be floated).
-A
-A
0
8
0-7
-A
-DQ
-DQ
(see DC Characteristics) produce spurious results and should not be attempted.
4
15
: Column Address. Selects 1 of 16 bit lines.
21
, and DQ
: Row Address. Selects 1 of 2048 word lines.
: Block Address.
7
15
:Inputs data and commands during CUI write cycles; outputs data during memory
:Inputs data during CUI write cycles in x16 mode; outputs data during memory
8-15
float. BYTE# V
Table 2. Pin Descriptions
0
# or CE
0
IL
IH
LHF32KZP
# and CE
places device in x8 mode. All data is then input or output on
1
enables normal operation. When driven V
# V
CC
IL
IH
PP
). Data is internally latched during a write cycle.
≤V
IH
Name and Function
deselects the device and reduces power consumption
≤V
1
places the device in x16 mode , and turns off the A
LKO
# must be V
PPLK
CC
, all write attempts to the flash memory are
voltage (see DC Characteristics) produce
, memory contents cannot be altered. Block
IL
to select the devices.
IL ,
Locked blocks can not be
IL
, RP# inhibits
Rev. 1.6
0
5