LH28F320S5HNS-ZP Sharp Electronics, LH28F320S5HNS-ZP Datasheet - Page 9

• Manufacturer Part Number: LH28F320S5HNS-ZP
• Manufacturer: Sharp Electronics

Specifications of LH28F320S5HNS-ZP

• Cell Type: NOR
• Density: 32Mb
• Access Time (max): 100ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 22/21Bit
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: -40C to 85C
• Package Type: SSOP
• Program/erase Volt (typ): 4.5 to 5.5V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8/16Bit
• Number Of Words: 4M/2M
• Supply Current: 75mA
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / Rohs Status: Compliant

2 PRINCIPLES OF OPERATION
The LH28F320S5HNS-ZP Flash memory includes an
on-chip WSM to manage block erase, full chip erase,
(multi)
configuration functions. It allows for: 100% TTL-level
control inputs, fixed power supplies during block
erase, full chip erase, (multi) word/byte write and
block lock-bit configuration, and minimal processor
overhead with RAM-Like interface timings.
After initial device power-up or return from deep
power-down mode (see Bus Operations), the device
defaults to read array mode. Manipulation of external
memory control pins allow array read, standby, and
output disable operations.
Status register, query structure and identifier codes
can be accessed through the CUI independent of the
V
block erase, full chip erase, (multi) word/byte write
and
associated with altering memory contents⎯block
erase, full chip erase, (multi) word/byte write and
block
identifier codes⎯are accessed via the CUI and
verified through the status register.
Commands
microprocessor write timings. The CUI contents serve
as input to the WSM, which controls the block erase,
full chip erase, (multi) word/byte write and block lock-
bit
regulated by the WSM, including pulse repetition,
internal
Addresses and data are internally latch during write
cycles. Writing the appropriate command outputs
array data, accesses the identifier codes, outputs
query structure or outputs status register data.
PP
voltage. High voltage on V
configuration.
block
lock-bit configuration, status, query and
word/byte
verification,
lock-bit
are
The
write
configuration.
written
and
internal
and
margining
PP
enables successful
using
algorithms
block
All
of
functions
standard
lock-bit
data.
are
LHF32KZP
Interface software that initiates and polls progress of
block erase, full chip erase, (multi) word/byte write
and block lock-bit configuration can be stored in any
block. This code is copied to and executed from
system RAM during flash memory updates. After
successful completion, reads are again possible via
the Read Array command. Block erase suspend
allows system software to suspend a block erase to
read or write data from any other block. Write
suspend allows system software to suspend a (multi)
word/byte write to read data from any other flash
memory array location.
2.1 Data Protection
Depending on the application, the system designer
may choose to make the V
switchable (available only when block erase, full chip
erase, (multi) word/byte write and block lock-bit
configuration are required) or hardwired to V
The device accommodates either design practice and
encourages optimization of the processor-memory
interface.
When V
altered. The CUI, with multi-step block erase, full chip
erase, (multi) word/byte write and block lock-bit
configuration
protection from unwanted operations even when high
voltage is applied to V
disabled when V
V
locking capability provides additional protection from
inadvertent code or data alteration by gating block
erase, full chip erase and (multi) word/byte write
operations.
LKO
or when RP# is at V
PP
≤V
PPLK
command
CC
, memory contents cannot be
is below the write lockout voltage
PP
. All write functions are
sequences,
IL
. The device’s block
PP
power supply
provides
Rev. 1.6
PPH1
6
.