MT48LC2M32B2TG-6 Micron Technology Inc, MT48LC2M32B2TG-6 Datasheet - Page 12
![no-image](/images/manufacturer_photos/0/4/441/micron_technology_inc_sml.jpg)
MT48LC2M32B2TG-6
Manufacturer Part Number
MT48LC2M32B2TG-6
Description
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet
1.MT48LC2M32B2TG-6.pdf
(69 pages)
Specifications of MT48LC2M32B2TG-6
Organization
2Mx32
Density
64Mb
Address Bus
13b
Access Time (max)
17/7.5/5.5ns
Maximum Clock Rate
166MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
180mA
Pin Count
86
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MT48LC2M32B2TG-6
Manufacturer:
MICRON
Quantity:
10
Company:
Part Number:
MT48LC2M32B2TG-6
Manufacturer:
MICRON
Quantity:
5
Part Number:
MT48LC2M32B2TG-6
Manufacturer:
MICRONAS
Quantity:
20 000
Part Number:
MT48LC2M32B2TG-6:G
Manufacturer:
MT
Quantity:
20 000
Part Number:
MT48LC2M32B2TG-6D
Manufacturer:
MICRON/美光
Quantity:
20 000
Company:
Part Number:
MT48LC2M32B2TG-6G
Manufacturer:
LT
Quantity:
4 330
Part Number:
MT48LC2M32B2TG-6G
Manufacturer:
MICRON/美光
Quantity:
20 000
Part Number:
MT48LC2M32B2TG-6IT
Manufacturer:
MICRON/美光
Quantity:
20 000
Register Definition
Mode Register
Burst Length
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5
64MSDRAMx32_2.fm - Rev. J 12/08 EN
The mode register is used to define the specific mode of operation of the SDRAM. This
definition includes the selection of a burst length, a burst type, a CL, an operating mode
and a write burst mode, as shown in Figure 4 on page 13. The mode register is
programmed via the LOAD MODE REGISTER command and will retain the stored infor-
mation until it is programmed again or the device loses power.
Mode register bits M0–M2 specify the burst length, M3 specifies the type of burst
(sequential or interleaved), M4–M6 specify the CL, M7, and M8 specify the operating
mode, M9 specifies the write burst mode, and M10 is reserved for future use.
The mode register must be loaded when all banks are idle, and the controller must wait
the specified time before initiating the subsequent operation. Violating either of these
requirements will result in unspecified operation.
Read and write accesses to the SDRAM are burst oriented, with the burst length being
programmable, as shown in Figure 4. The burst length determines the maximum
number of column locations that can be accessed for a given READ or WRITE command.
Burst lengths of 1, 2, 4, or 8 locations are available for both the sequential and the inter-
leaved burst types, and a full-page burst is available for the sequential type. The full-
page burst is used in conjunction with the BURST TERMINATE command to generate
arbitrary burst lengths.
Reserved states should not be used, as unknown operation or incompatibility with
future versions may result.
When a READ or WRITE command is issued, a block of columns equal to the burst
length is effectively selected. All accesses for that burst take place within this block,
meaning that the burst will wrap within the block if a boundary is reached. The block is
uniquely selected by A1–A7 when BL = 2; by A2–A7 when BL = 4; and by A3–A7 when the
BL = 8. The remaining (least significant) address bit(s) is (are) used to select the starting
location within the block. Full-page bursts wrap within the page if the boundary is
reached.
12
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Functional Description
©2001 Micron Technology, Inc. All rights reserved.
64Mb: x32 SDRAM