MT48LC2M32B2TG-6 Micron Technology Inc, MT48LC2M32B2TG-6 Datasheet - Page 33
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MT48LC2M32B2TG-6
Manufacturer Part Number
MT48LC2M32B2TG-6
Description
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet
1.MT48LC2M32B2TG-6.pdf
(69 pages)
Specifications of MT48LC2M32B2TG-6
Organization
2Mx32
Density
64Mb
Address Bus
13b
Access Time (max)
17/7.5/5.5ns
Maximum Clock Rate
166MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
180mA
Pin Count
86
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MT48LC2M32B2TG-6
Manufacturer:
MICRON
Quantity:
10
Company:
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MT48LC2M32B2TG-6
Manufacturer:
MICRON
Quantity:
5
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Manufacturer:
MICRONAS
Quantity:
20 000
Part Number:
MT48LC2M32B2TG-6:G
Manufacturer:
MT
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20 000
Part Number:
MT48LC2M32B2TG-6D
Manufacturer:
MICRON/美光
Quantity:
20 000
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Part Number:
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Manufacturer:
LT
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MT48LC2M32B2TG-6IT
Manufacturer:
MICRON/美光
Quantity:
20 000
Power-Down
Figure 22:
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5
64MSDRAMx32_2.fm - Rev. J 12/08 EN
Terminating a WRITE Burst
Note:
Power-down occurs if CKE is registered LOW coincident with a NOP or COMMAND
INHIBIT when no accesses are in progress (see Figure 24 on page 34). If power-down
occurs when all banks are idle, this mode is referred to as precharge power-down; if
power-down occurs when there is a row active in either bank, this mode is referred to as
active power-down. Entering power-down deactivates the input and output buffers,
excluding CKE, for maximum power savings while in standby. The device may not
remain in the power-down state longer than the refresh period (
refresh operations are performed in this mode.
The power-down state is exited by registering an NOP or COMMAND INHIBIT and CKE
HIGH at the desired clock edge (meeting
COMMAND
ADDRESS
DQMs are LOW.
CLK
DQ
BANK,
WRITE
COL n
D
T0
n
IN
TERMINATE
BURST
T1
DON’T CARE
COMMAND
(ADDRESS)
(DATA)
T2
NEXT
33
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
CKS).
©2001 Micron Technology, Inc. All rights reserved.
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64Mb: x32 SDRAM
REF or
t
REF
Commands
AT
) since no