CY7C0832V-167AC Cypress Semiconductor Corp, CY7C0832V-167AC Datasheet - Page 16

• Manufacturer Part Number: CY7C0832V-167AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C0832V-167AC

• Density: 4.5Mb
• Access Time (max): 4ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 167MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 18b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 2
• Supply Current: 300mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 120
• Word Size: 18b
• Number Of Words: 256K
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-06059 Rev. *K
Switching Waveforms
Read Cycle
Notes:
29. OE is asynchronously controlled; all other inputs (excluding MRST and JTAG) are synchronous to the rising clock edge.
30. ADS = CNTEN = LOW, and MRST = CNTRST = CNT/MSK = HIGH.
31. The output is disabled (high-impedance state) by CE = V
32. Addresses do not have to be accessed sequentially since ADS = CNTEN = V
Master Reset
MRST
ALL
ADDRESS/
DATA
LINES
ALL
OTHER
INPUTS
TMS
CNTINT
INT
TDO
Numbers are for reference only.
ADDRESS
DATA
BE0–BE1
R/W
CLK
OUT
OE
[11, 29, 30, 31, 32]
CE
t
RSF
t
t
t
t
SB
SW
SA
SC
A
t
RS
n
t
t
t
t
INACTIVE
RSS
t
HB
HW
HA
t
HC
CH2
1 Latency
t
RSR
t
CYC2
t
CKLZ
t
CL2
IH
PRELIMINARY
A
n+1
following the next rising edge of the clock.
ACTIVE
t
CD2
IL
with CNT/MSK = V
Q
A
n
n+2
IH
constantly loads the address on the rising edge of the CLK.
t
DC
CY7C0830V/CY7C0831V
CY7C0832V/CY7C0833V
Q
t
SC
n+1
t
OHZ
A
n+3
t
OLZ
t
HC
CY7C0837V
t
OE
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Q
n+2