CY7C0832V-167AC Cypress Semiconductor Corp, CY7C0832V-167AC Datasheet - Page 17

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CY7C0832V-167AC

Manufacturer Part Number
CY7C0832V-167AC
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C0832V-167AC

Density
4.5Mb
Access Time (max)
4ns
Sync/async
Synchronous
Architecture
SDR
Clock Freq (max)
167MHz
Operating Supply Voltage (typ)
3.3V
Address Bus
18b
Package Type
TQFP
Operating Temp Range
0C to 70C
Number Of Ports
2
Supply Current
300mA
Operating Supply Voltage (min)
3.135V
Operating Supply Voltage (max)
3.465V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
120
Word Size
18b
Number Of Words
256K
Lead Free Status / Rohs Status
Not Compliant
Document #: 38-06059 Rev. *K
Switching Waveforms
Bank Select Read
Notes:
33. In this depth-expansion example, B1 represents Bank #1 and B2 is Bank #2; each bank consists of one Cypress FLEx18 device from this data sheet. ADDRESS
34.
35. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals.
36. During “No Operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.
37.
38. CE
ADDRESS
ADDRESS
Read-to-Write-to-Read (OE = LOW)
DATA
DATA
ADDRESS
DATA
= ADDRESS
completed (labelled as no operation). One clock cycle is required to three-state the I/O for the Write operation on the next rising edge of CLK.
DATA
ADS = CNTEN= BE0 – BE1 = OE = LOW; MRST = CNTRST = CNT/MSK = HIGH.
CE
OUT(B2)
0
OUT(B1)
CE
CE
0
CLK
R/W
= BE0 – BE1 = R/W = LOW; CE
OUT
= OE = BE0 – BE1 = LOW; CE
CE
CLK
(B1)
(B1)
(B2)
IN
(B2)
(B2)
t
t
t
SW
SC
SA
t
t
t
t
.
SA
SC
SA
SC
[33, 34]
A
n
A
A
0
t
0
CH2
t
CH2
t
(continued)
t
CYC2
t
t
HW
HC
HA
t
t
t
t
t
CYC2
HA
HC
HA
HC
1
1
= R/W = CNTRST = MRST = HIGH.
= CNTRST = MRST = CNT/MSK = HIGH. When R/W first switches low, since OE = LOW, the Write operation cannot be
t
CL2
t
CL2
[32, 35, 36, 37, 38]
A
READ
n+1
A
A
t
CD2
1
1
t
CD2
PRELIMINARY
t
SW
t
Q
SC
n
Q
A
t
0
SC
n+2
t
A
CKHZ
A
NO OPERATION
2
2
t
t
DC
HC
t
HW
t
HC
t
CD2
t
SD
A
D
n+2
n+2
Q
t
A
A
HD
1
3
t
3
DC
t
t
CKLZ
CKHZ
WRITE
t
CD2
CY7C0830V/CY7C0831V
CY7C0832V/CY7C0833V
A
n+3
Q
A
A
4
2
4
t
t
t
CKHZ
CD2
CKLZ
READ
t
CKLZ
CY7C0837V
Q
3
A
n+4
Page 17 of 28
A
t
A
CD2
5
t
5
CKLZ
t
t
CKHZ
CD2
Q
n+3
(B1)
Q
4

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