CY7C67200-48BAI Cypress Semiconductor Corp, CY7C67200-48BAI Datasheet - Page 2

• Manufacturer Part Number: CY7C67200-48BAI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C67200-48BAI

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: FBGA
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-08014 Rev. *G
Introduction
EZ-OTG™ (CY7C67200) is Cypress Semiconductor’s first
USB On-The-Go (OTG) host/peripheral controller. EZ-OTG is
designed to easily interface to most high-performance CPUs
to add USB host functionality. EZ-OTG has its own 16-bit RISC
processor to act as a coprocessor or operate in standalone
mode. EZ-OTG also has a programmable IO interface block
allowing a wide range of interface options.
Processor Core Functional Overview
An overview of the processor core components are presented
in this section.
Processor
EZ-OTG has a general purpose 16-bit embedded RISC
processor that runs at 48 MHz.
Clocking
EZ-OTG requires a 12 MHz source for clocking. Either an
external crystal or TTL-level oscillator may be used. EZ-OTG
has an internal PLL that produces a 48 MHz internal clock from
the 12 MHz source.
Memory
EZ-OTG has a built-in 4K × 16 masked ROM and an 8K × 16
internal RAM. The masked ROM contains the EZ-OTG BIOS.
The internal RAM can be used for program code or data.
Table 1. Interface Options for GPIO Pins
GPIO31
GPIO30
GPIO29
GPIO24
GPIO23
GPIO22
GPIO21
GPIO20
GPIO19
GPIO15
GPIO14
GPIO13
GPIO12
GPIO11
GPIO10
GPIO9
GPIO8
GPIO7
GPIO6
GPIO5
GPIO4
GPIO3
GPIO2
GPIO1
GPIO0
GPIO Pins
nWR
nRD
nCS
D15
D14
D13
D12
D11
D10
HPI
INT
A1
A0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
HSS
RXD
CTS
RTS
TXD
MOSI
MISO
nSSI
SCK
SPI
Interrupts
EZ-OTG provides 128 interrupt vectors. The first 48 vectors
are hardware interrupts and the following 80 vectors are
software interrupts.
General Timers and Watchdog Timer
EZ-OTG has two built-in programmable timers and a
watchdog timer. All three timers can generate an interrupt to
the EZ-OTG.
Power Management
EZ-OTG has one main power-saving mode, Sleep. Sleep
mode pauses all operations and provides the lowest power
state.
Interface Descriptions
EZ-OTG has a variety of interface options for connectivity, with
several interface options available. See
how the interfaces share pins and can coexist. Below are
some general guidelines:
• I2C EEPROM and OTG do not conflict with any interfaces
• HPI is mutually exclusive to HSS, SPI, and UART
UART
RX
TX
SCL/SDA
SCL/SDA
I2C
Table 1
CY7C67200
to understand
Page 2 of 78
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