CY7C67200-48BAI Cypress Semiconductor Corp, CY7C67200-48BAI Datasheet - Page 71

• Manufacturer Part Number: CY7C67200-48BAI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C67200-48BAI

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: FBGA
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-08014 Rev. *G
HSS BYTE Mode Transmit
qt_clk, CPU_A, CPUHSS_cs, CPU_wr are internal signals, included in the diagram to illustrate relationship between CPU opera-
tions and HSS port operations.
Bit 0 is LSB of data byte. Data bits are HIGH true: HSS_TxD HIGH = data bit value ‘1’.
BT = bit time = 1/baud rate.
HSS Block Mode Transmit
BLOCK mode transmit timing is similar to BYTE mode, except the STOP bit time is controlled by the HSS_GAP value.
The BLOCK mode STOP bit time, t
Transmit Gap register 90xC074].
The default t
BT = bit time = 1/baud rate.
HSS BYTE and BLOCK Mode Receive
Receive data arrives asynchronously relative to the internal clock.
Incoming data bit rate may deviate from the programmed baud rate clock by as much as ±5% (with HSS_RATE value of 23 or
higher).
BYTE mode received bytes are buffered in a FIFO. The FIFO not empty condition becomes the RxRdy flag.
BLOCK mode received bytes are written directly to the memory system.
Bit 0 is LSB of data byte. Data bits are HIGH true: HSS_RxD HIGH = data bit value ‘1’.
BT = bit time = 1/baud rate.
CPU_A[2:0]
CPUHSS_cs
TxRdy flag
HSS_TxD
CPU_wr
qt_clk
HSS_RxD
HSS_TxD
GAP
is 2 BT.
Byte transmit
triggered by a
CPU write to the
HSS_TxData register
BT +/- 5%
start bit
BT +/- 5%
bit 0
GAP
= (HSS_GAP – 9) BT, where BT is the bit time, and HSS_GAP is the content of the HSS
TxRdy low to start bit delay:
0 min, BT max when starting from IDEL.
(BT = bit period)
bit 1
For back to back transmit, new START Bit
begins immediately following previous STOP bit.
bit 2
start bit
BT
BT
BT
bit 0
bit 3
10 BT +/- 5%
bit 1
t
GAP
bit 4
bit 2
bit 5
bit 3
received byte added to
receive FIFO during the final data bit time
bit 4
start of last data bit to TxRdy high:
0 min, 4 T max.
(T is qt_clk period)
bit 6
bit 5
bit 7
bit 6
stop bit
CY7C67200
goes high
bit 7
CPU may start another BYTE
transmit right after TxRdy
Page 71 of 78
start bit
stop bit
1 stop bit shown.
1 or 2 stop bits.
programmable
start bit
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