CYNSE70064A-66BGC Cypress Semiconductor Corp, CYNSE70064A-66BGC Datasheet - Page 109

• Manufacturer Part Number: CYNSE70064A-66BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70064A-66BGC

• Operating Supply Voltage (typ): 1.8V
• Operating Supply Voltage (min): 1.7V
• Operating Supply Voltage (max): 1.9V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

12.6
SRAM Write enables Write access to the off-chip SRAM that contains associative data. The latency from the second cycle of the
Write instruction to the address appearing on the SRAM bus is the same as the latency of the Search instruction, and will depend
on the TLSZ value parameter programmed in the device configuration register. The following explains the SRAM Write operation
accomplished through a table of only one device with the following parameters: TLSZ = 00, HLAT = 000, LRAM = 1, and
LDEV = 1. Figure 12-8 shows the timing diagram. For the following description the selected device refers to the only device in
the table as it is the only device that will be accessed.
At the end of cycle 3, a new command can begin. The Write is a pipelined operation, however the Write cycle appears at the
SRAM bus with the same latency as the latency of Search instruction as measured from the second cycle of the Write command.
Document #: 38-02041 Rev. *F
• Cycle 1A: The host ASIC applies the Write instruction on the CMD[1:0], using CMDV = 1. The DQ bus supplies the address
• Cycle 1B: The host ASIC continues to apply the Write instruction on the CMD[1:0], using CMDV = 1. The DQ bus supplies
• Cycle 2: The host ASIC continues to drive DQ[67:0]. The data in this cycle is not used by the CYNSE70064A.
• Cycle 3: The host ASIC continues to drive DQ[67:0]. The data in this cycle is not used by the CYNSE70064A.
with DQ[20:19] set to 10 to select the SRAM address. The host ASIC selects the device for which the ID[4:0] matches the
DQ[25:21] lines. The host ASIC also supplies SADR[21:20] on CMD[8:7] in this cycle. Note. CMD[2] must be set to 0 for SRAM
Write as burst Writes into the SRAM are not supported.
the address with DQ[20:19] set to 10 to select the SRAM address. Note that CMD[2] must be set to 0 for SRAM Write as burst
Writes into the SRAM are not supported.
SRAM Write with a Table of One Device
SADR[21:0]
CMD[8:2]
CMD[1:0]
TLSZ = 10, HLAT = 010, LRAM = 1, LDEV = 1
PHS_L
CMDV
CLK2X
ACK
ALE_L
OE_L
CE_L
SSV
WE_L
SSF
DQ
Figure 12-7. SRAM Read Through Device Number 0 in Bank of 31 Devices
0
1
1
z
0
0
1
Address
cycle
Read
1
A B
00
cycle
(Device Number 30 Timing)
2
cycle
3
cycle
4
cycle
5
cycle
6
cycle
7
z
z
z
z
cycle
8
1
1
1
cycle
9
cycle
10
CYNSE70064A
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