CYNSE70064A-66BGC Cypress Semiconductor Corp, CYNSE70064A-66BGC Datasheet - Page 97

no-image

CYNSE70064A-66BGC

Manufacturer Part Number
CYNSE70064A-66BGC
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CYNSE70064A-66BGC

Operating Supply Voltage (typ)
1.8V
Operating Supply Voltage (min)
1.7V
Operating Supply Voltage (max)
1.9V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Package Type
BGA
Mounting
Surface Mount
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CYNSE70064A-66BGC
Manufacturer:
CY
Quantity:
44
Part Number:
CYNSE70064A-66BGC
Manufacturer:
CYPRESS
Quantity:
329
Part Number:
CYNSE70064A-66BGC
Manufacturer:
ALTERA
0
Part Number:
CYNSE70064A-66BGC
Manufacturer:
CYPRESS
Quantity:
7
Part Number:
CYNSE70064A-66BGC
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Table 10-34. The Latency of SRAM Write Cycle from Second Cycle of Learn Instruction
The Learn operation lasts two CLK cycles. The sequence of operation is as follows.
At the end of cycle 2, a new instruction can begin. The latency of the SRAM Write is the same as the Search to the SRAM Read
cycle. It is measured from the second cycle of the Learn instruction.
Document #: 38-02041 Rev. *F
• Cycle 1A: The host ASIC applies the Learn instruction on CMD[1:0] using CMDV = 1. The CMD[5:2] field specifies the index
• Cycle 1B: The host ASIC continues to drive the CMDV to 1, the CMD[1:0] to 11, and the CMD[5:2] with the comparand pair
• Cycle 2: The host ASIC drives the CMDV to 0.
of the comparand register pair that will be written in the data array in the 136-bit-configured table. For a Learn in a 68-bit-con-
figured table, the even-numbered comparand specified by this index will be written. CMD[8:7] carries the bits that will be driven
on SADR[21:20] in the SRAM Write cycle.
index. CMD[6] must be set to 0 if the Learn is being performed on a 68-bit-configured table, and to 1 if the Learn is being
performed on a 136-bit-configured table.
Number of Devices
1–31 (TLSZ = 10)
1–8 (TLSZ = 01)
1 (TLSZ = 00)
SADR[21:0]
CMD[1:0]
CMD[8:2]
CLK2X
PHS_L
CMDV
TLSZ = 01, LRAM = 1, LDEV = 1.
WE_L
OE_L
CE_L
SSV
SSF
Figure 10-75. Timing Diagram of Learn on Device Number 7 (TLSZ = 01)
DQ
z
z
1
1
0
0
0
Comp1
cycle
Learn1
1A 1B
1
X
cycle
2
X
X
X
X
cycle
Comp2
Learn2
3
X
cycle
4
X
X
X
X
cycle
5
z
cycle
Latency in CLK Cycles
1
6
cycle
z
7
z
z
cycle
4
5
6
8
1
1
cycle
z
9
z
z
cycle
10
z
1
1
0
CYNSE70064A
Page 97 of 128

Related parts for CYNSE70064A-66BGC