CYNSE70128-83BGC Cypress Semiconductor Corp, CYNSE70128-83BGC Datasheet - Page 124

• Manufacturer Part Number: CYNSE70128-83BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70128-83BGC

• Operating Supply Voltage (min): 1.425V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

14.0
Figure 14-1 shows how an NSE subsystem can be formed using a host ASIC and an CYNSE70128 bank. It also shows how this
NSE subsystem is integrated in a switch or router. The CYNSE70128 can access synchronous and asynchronous SRAMs by
allowing the host ASIC to set the same HLAT parameter in all NSEs within a bank of NSEs.
15.0
The CYNSE70128 supports the Test Access Port and Boundary Scan Architecture as specified in the IEEE JTAG standard
number 1149.1. The pin interface to the chip consists of five signals with the standard definitions: TCK, TMS, TDI, TDO, and
TRST_L. Table 15-1 describes the operations that the test access port controller supports, and Table 15-2 describes the TAP
Device ID Register.
TRST_L to ground through a pull-down.
Table 15-1. Supported Operations
Document #: 38-02040 Rev. *F
SAMPLE/PRELOAD Mandatory This operation loads the values of signals going to and from I/O pins into the boundary scan
EXTEST
BYPASS
IDCODE
CLAMP
HighZ
Instruction
Application
JTAG (1149.1) Testing
Note
Mandatory This operation uses boundary scan values shifted in from TAP to test connectivity external to
Mandatory This operation loads a single bit shift register between TDI and TDO and provides a minimum-
Optional
Optional
Optional
. To disable JTAG functionality, connect the TCK, TMS and TDI pins to V
Type
Figure 14-1. Sample Switch/Router Using the CYNSE70128 Device
shift register to provide a snapshot of the normal functional operation.
the device.
length serial path when no test operation is required
This operation selects the Identification register between TDI and TDO and allows the “idcode”
to be read serially through TDO.
This operation drives preset values onto the outputs of devices.
This operation leaves the device output pins in a high-impedance state.
Description
DDQ
through a pull-up, and
CYNSE70128
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