CYNSE70128-83BGC Cypress Semiconductor Corp, CYNSE70128-83BGC Datasheet - Page 50

• Manufacturer Part Number: CYNSE70128-83BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70128-83BGC

• Operating Supply Voltage (min): 1.425V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

The logical 72-bit Search operation is shown in Figure 10-26. The entire table (31 devices of 72-bit entries) is compared to a 72-
bit word K (presented on the DQ bus in both cycles A and B of the command) using the GMR and the local mask bits. The effective
GMR is the 72-bit word specified by the identical value in both even and odd GMR pairs in each of the eight devices and selected
by the GMR Index in the command’s cycle A. The 72-bit word K (presented on the DQ bus in both cycles A and B of the command)
is also stored in both even and odd comparand register pairs in each of the eight devices and selected by the Comparand Register
Index in command’s cycle B. In the x72 configuration, the even comparand register can be subsequently used by the Learn
command only in the first non-full device. The word K (presented on the DQ bus in both cycles A and B of the command) is
compared with each entry in the table starting at location 0. The first matching entry’s location address L is the winning address
that is driven as part of the SRAM address on the SADR[23:0] lines (see “SRAM Addressing” on page 105). The global winning
device will drive the bus in a specific cycle. On global miss cycles the device with LRAM = 1 and LDEV = 1 will be the default
driver for such missed cycles.
The Search command is a pipelined operation and executes a search at half the rate of the frequency of CLK2X for 72-bit searches
in x72-configured tables. The latency of SADR, CE_L, ALE_L, WE_L, SSV, and SSF from the 72-bit Search command cycle (two
CLK2X cycles) is shown in Table 10-16.
Table 10-16. The Latency of Search from Instruction to SRAM Access Cycle
For up to 31 devices in the table (TLSZ = 10), search latency from command to SRAM access cycle is 6. In addition, SSV and
SSF shift further to the right for different values of HLAT, as specified in Table 10-17.
Table 10-17. Shift of SSF and SSV from SADR
Document #: 38-02040 Rev. *F
Number of Devices
1–31 (TLSZ = 10)
1–8 (TLSZ = 01)
1 (TLSZ = 00)
HLAT
000
001
010
011
100
101
110
111
Must be same in each of the 31
Will be same in each of the 31
Comparand Register (odd)
Comparand Register (even)
71
devices
devices
K
K
Figure 10-26. x72 Table with 31 Devices
Max Table Size
1984K × 72 bits
512K × 72 bits
64K × 72 bits
0
2031615
Location
address
L
0
1
2
3
CFG = 0000000000000000
71
71
(72-bit configuration)
Number of CLK Cycles
GMR
K
0
1
2
3
4
5
6
7
0
0
(First matching entry)
Latency in CLK Cycles
4
5
6
CYNSE70128
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